FPGA之verilog学习第一天（时分秒数字时钟）

module data_clock
(
input i_sys_clk,
input i_sys_rstn,
output [3:0] shi,
output [5:0]fen,
output [5:0] miao
);


//miao cnt;
reg [5:0] miao_cnt;
always@(posedge i_sys_clk or negedge i_sys_rstn)begin
if(i_sys_rstn==1'b0)begin
miao_cnt <= 6'd0;
end
else if(miao_cnt==6'd60)begin
miao_cnt <= 6'd0;
end
else begin
miao_cnt <= miao_cnt + 1'b1;
end
end


//fen cnt;
reg [5:0] fen_cnt;
always@(posedge i_sys_clk or negedge i_sys_rstn)begin
if(i_sys_rstn==1'b0)begin
fen_cnt <= 6'd0 ;
end
else if(fen_cnt==6'd60)begin
fen_cnt <= 6'd0 ;
end
else begin
fen_cnt <= fen_cnt + 1'b1;
end
end


//shi cnt;
reg [3:0] shi_cnt;
always@(posedge i_sys_clk or negedge i_sys_rstn)begin
if(i_sys_rstn==1'b0)begin
shi_cnt <= 4'd0;
end
else if(shi_cnt==4'd12)begin
shi_cnt <= 4'd0;
end
else begin
shi_cnt <= shi_cnt + 1'b1;
end
end


assign shi = shi_cnt;
assign fen = fen_cnt;
assign miao = miao_cnt;


endmodule