FPGA 设计32位乘法器

实验代码

module mul_32(out,a,b);

  input[31:0]a,b;
  output[63:0]out;
  wire[63:0]out;
  assign out=a*b;

endmodule

module mul_32(out,a,b);
  input[31:0]a,b;
  output[63:0]out;
  wire[63:0]out;
  assign out=a*b;
endmodule

测试代码

`timescale 100ps/100ps
module mul_32_tb;
  reg[31:0]a,b;
  wire[63:0]out;
  mul_32 uut(.a(a),
             .b(b),
             .out(out)
             );
initial begin
  a=32'b0;
  b=32'b0;
  forever #20
  begin
    a=($random);
    b=($random);
end
end
endmodule

`timescale 100ps/100ps
module mul_32_tb;
  reg[31:0]a,b;
  wire[63:0]out;
  mul_32 uut(.a(a),
             .b(b),
             .out(out)
             );
initial begin
  a=32'b0;
  b=32'b0;
  forever #20
  begin
    a=($random);
    b=($random);
end
end
endmodule