STM32使用内部高速振荡器(HSI)通过锁相环PLL倍频到64MHZ之寄存器实现方式

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STM32使用内部高速振荡器(HSI)通过锁相环PLL倍频到64MHZ之库函数实现方式

获取STM32系统各时钟频率

一、配置系统时钟

/***************************************************************
*函数名: vSystem_Clock_Config
*描  述: 配置系统时钟
*说  明: 将HSI通过PLL倍频到64MHZ
*注  意: HSI通过PLL倍频最大只能倍频到64MHZ
***************************************************************/
void vSystem_Clock_Config(void)
{
	u32 startUpCount = 0, status = 0;

	
	RCC->CR |= (u32)0x00000001;//Resets RCC default state 
	RCC->CR |= ((u32)RCC_CR_HSION);//Enable HSI
	do//Wait till HSI is ready and if Time out is reached exit
	{
		status = RCC->CR & RCC_CR_HSIRDY;
		startUpCount++;  
	} while((status == 0) && (startUpCount != HSE_STARTUP_TIMEOUT));

	if(status)
	{
		FLASH->ACR |= FLASH_ACR_PRFTBE;//Enable Prefetch Buffer
		
		//Flash 2 wait state
		FLASH->ACR &= (u32)((u32)~FLASH_ACR_LATENCY);
		FLASH->ACR |= (u32)FLASH_ACR_LATENCY_2;    

		RCC->CFGR |= (u32)RCC_CFGR_HPRE_DIV1;//HCLK = SYSCLK
		RCC->CFGR |= (u32)RCC_CFGR_PPRE2_DIV1;//PCLK2 = HCLK 
		RCC->CFGR |= (u32)RCC_CFGR_PPRE1_DIV2;//PCLK1 = HCLK

		//PLL configuration: PLLCLK = HSI/2 * 16 = 64 MHz
		RCC->CFGR &= (u32)((u32)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
		RCC->CFGR |= (u32)(RCC_CFGR_PLLSRC_HSI_Div2| RCC_CFGR_PLLMULL16);

		RCC->CR |= RCC_CR_PLLON;//Enable PLL
		while((RCC->CR & RCC_CR_PLLRDY) == 0);//Wait till PLL is ready

		//Select PLL as system clock source
		RCC->CFGR &= (u32)((u32)~(RCC_CFGR_SW));
		RCC->CFGR |= (u32)RCC_CFGR_SW_PLL;    
		while ((RCC->CFGR & (u32)RCC_CFGR_SWS) != (u32)0x08);//Wait till PLL is used as system clock source 
	}
	else
	{
		
	}
}

注意：
1.STM32系列HSI通过PLL倍频最大只能倍频到64MHZ。

二、打印输出系统各时钟频率

RCC_ClocksTypeDef RCC_CLK;

int main(void)
{	
	vSystem_Init();
	
	RCC_GetClocksFreq(&RCC_CLK);//Get chip frequencies
	#if ( USE_SEGGER_RTT_ENABLE > 0 )//Use segger rtt enable
	SEGGER_RTT_printf(0, "System Clock Source : %d\r\n", RCC_GetSYSCLKSource());
	SEGGER_RTT_printf(0, "APB1/PCLK1 : %dHZ\r\n", RCC_CLK.PCLK1_Frequency);
	SEGGER_RTT_printf(0, "APB2/PCLK2 : %dHZ\r\n", RCC_CLK.PCLK2_Frequency);
	SEGGER_RTT_printf(0, "SYSCLK     : %dHZ\r\n", RCC_CLK.SYSCLK_Frequency);
	SEGGER_RTT_printf(0, "HCLK       : %dHZ\r\n", RCC_CLK.HCLK_Frequency);
	#endif

	
	while(1)
	{
		vKeyBoard_Service_Handle();
		PAout(6) = 0;
		vDelay_ms(100);
		PAout(6) = 1;
		vDelay_ms(1000);
	}
}

三、系统初始化vSystem_Init()

static void vSystem_Init(void)
{
	SystemInit();
	vSystem_Clock_Config();
	vSysTick_Init();
	NVIC_PriorityGroupConfig(NVIC_PriorityGroup_4);
	vTIM_Init();
	vLCD1602_Init();
	LED_Init();
	vKEY_GPIO_Config();
	
		
	#if ( USE_SEGGER_RTT_ENABLE > 0 )//Use segger rtt enable
	SEGGER_RTT_Init();
	SEGGER_RTT_printf(0, "Build Times: %s  %s\r\n", __DATE__, __TIME__);
	SEGGER_RTT_printf(0, "STM32F103xx Start Running......\r\n\r\n");
	#endif
	
	#if ( USE_KEIL_MACRO_INFO_ENBALE > 0 )//Use Keil macro information enable 
	vKeil_Macro_Information();
	#endif	
}

四、运行结果

00> Build Times: Mar 14 2020  10:11:21
00> STM32F103xx Start Running......
00> 
00> System Clock Source : 8
00> APB1/PCLK1 : 64000000HZ
00> APB2/PCLK2 : 64000000HZ
00> SYSCLK     : 64000000HZ
00> HCLK       : 64000000HZ