FPGA学习（一） 实现简易秒表（无按键）

刚开始接触FPGA，用FPGA实现了一个简易秒表（没有按键），以此来记录一下我学习的过程。

功能：

   六个数码管显示时、分、秒

module jianyimiaobiao(clk,rst,sg,sg_d);
input clk;
input rst;
output sg;
output sg_d;

reg [25:0] count_1s;
reg [5:0] count_60s;
reg [5:0] count_60m;
reg [4:0] count_24h;
reg [5:0] count_1us;
reg [6:0] count_120us;
reg [5:0] sg;
reg [7:0] sg_d;

reg [7:0] h_g;
reg [7:0] h_s;
reg [7:0] m_g;
reg [7:0] m_s;
reg [7:0] s_g;
reg [7:0] s_s;
parameter _0 = 8'b1011_1111;
parameter _1 = 8'b1000_0110;
parameter _2 = 8'b1101_1011;
parameter _3 = 8'b1100_1111;
parameter _4 = 8'b1110_0110;
parameter _5 = 8'b1110_1101;
parameter _6 = 8'b1111_1101;
parameter _7 = 8'b1000_0111;
parameter _8 = 8'b1111_1111;
parameter _9 = 8'b1110_1111;

parameter _1s = 49_999_999;
parameter _1us = 49;
//1s计时器
always@(posedge clk or negedge rst)
   if(!rst)
	  count_1s <= 26'd0;
	else if( count_1s == _1s )
	  count_1s <=26'd0;
	else 
	  count_1s <= count_1s +1'b1;
//数码管动态扫描  位选
always@(posedge clk or negedge rst)
   if(!rst)
	  count_1us <=6'd0;
	else if(count_1us == _1us)
	  count_1us <=6'b0;
	else 
	  count_1us <= count_1us + 1'b1;
	
always@(posedge clk or negedge rst)
   if(!rst)
	  count_120us <=7'd0;
	else if(count_120us == 119 && count_1us == _1us)
	  count_120us <=7'd0;
	else if(count_1us == _1us)
	  count_120us <= count_120us + 1'b1;
 
always  @(posedge clk or negedge rst)
   if(!rst)
     sg<=6'b111_111;
   else if(count_120us==0)
     sg<=6'b111_110;
   else if(count_120us==19&&count_1us==_1us)
     sg<=6'b111_101;
   else if(count_120us==39&&count_1us==_1us)
     sg<=6'b111_011;
   else if(count_120us==59&&count_1us==_1us)
     sg<=6'b110_111;
   else if(count_120us==79&&count_1us==_1us)
     sg<=6'b101_111;
   else if(count_120us==99&&count_1us==_1us)
     sg<=6'b011_111;

//60s计时器
always@(posedge clk or negedge rst)
   if(!rst)
	  count_60s <= 6'd0;
	else if(count_60s == 59 && count_1s == _1s )
	  count_60s <= 6'b0;
	else if(count_1s == _1s)
	  count_60s <= count_60s + 1'b1;

always@(posedge clk or negedge rst)
   if(!rst)
	  s_g <= 4'd0;
	else if(sg==6'b111_110)
	 begin
	  case(count_60s%10)
	     0: s_g <= _0;
		  1: s_g <= _1;
		  2: s_g <= _2;
		  3: s_g <= _3;
		  4: s_g <= _4;
		  5: s_g <= _5;
		  6: s_g <= _6;
		  7: s_g <= _7;
		  8: s_g <= _8;
		  9: s_g <= _9;
	  endcase 
	 end
	
always@(posedge clk or negedge rst)
   if(!rst)
	  s_s <= 4'd0;
	else if(sg==6'b111_101)
	 begin
	  case(count_60s/10)
	     0: s_s <= _0;
		  1: s_s <= _1;
		  2: s_s <= _2;
		  3: s_s <= _3;
		  4: s_s <= _4;
		  5: s_s <= _5;
		  6: s_s <= _6;
	 endcase 
	end
//60m计时器
always@(posedge clk or negedge rst)
   if(!rst)
	  count_60m <= 6'd0;
	else if(count_60m == 59 && count_60s == 59 && count_1s == _1s)
	  count_60m <= 6'b0;
	else if(count_60s == 59 && count_1s == _1s)
	  count_60m <= count_60m + 1'b1;

always@(posedge clk or negedge rst)
   if(!rst)
	  m_g <= 4'd0;
	else if(sg==6'b111_011)
	 begin
	  case(count_60m%10)
	     0: m_g <= _0;
		  1: m_g <= _1;
		  2: m_g <= _2;
		  3: m_g <= _3;
		  4: m_g <= _4;
		  5: m_g <= _5;
		  6: m_g <= _6;
		  7: m_g <= _7;
		  8: m_g <= _8;
		  9: m_g <= _9;
	 endcase
	 end 

always@(posedge clk or negedge rst)
   if(!rst)
	  m_s <= 4'd0;
	else if(sg==6'b110_111)
	 begin
	  case(count_60m/10)
	     0: m_s <= _0;
		  1: m_s <= _1;
		  2: m_s <= _2;
		  3: m_s <= _3;
		  4: m_s <= _4;
		  5: m_s <= _5;
		  6: m_s <= _6;
	 endcase 
	 end 
//24h计时器
always@(posedge clk or negedge rst)
   if(!rst)
	  count_24h <= 5'd0;
	else if(count_24h == 23 && count_60m == 59 && count_60s == 59 && count_1s == _1s)
	  count_24h <= 5'd0;
	else if(count_60m == 59 && count_60s == 59 && count_1s == _1s)
	  count_24h <= count_24h + 1'b1; 

always@(posedge clk or negedge rst)
   if(!rst)
	  h_g <= 4'd0;
	else if(sg==6'b101_111)
	 begin
	  case(count_24h%10)
	     0: h_g <= _0;
		  1: h_g <= _1;
		  2: h_g <= _2;
		  3: h_g <= _3;
		  4: h_g <= _4;
		  5: h_g <= _5;
		  6: h_g <= _6;
		  7: h_g <= _7;
		  8: h_g <= _8;
		  9: h_g <= _9;
	  endcase 
	 end

always@(posedge clk or negedge rst)
   if(!rst)
	  h_s <= 4'd0;
	else if(sg==6'b011_111)
	 begin
	  case(count_24h/10)
	     0: h_s <= _0;
		  1: h_s <= _1;
		  2: h_s <= _2;
	 endcase
	 end 

 always@(posedge clk or negedge rst)
   if(!rst)
	  sg_d <= 6'b0;
	else 
	  begin
	   case(sg)
		  6'b111_110: sg_d <= s_g;
		  6'b111_101: sg_d <= s_s;
		  6'b111_011: sg_d <= m_g;
		  6'b110_111: sg_d <= m_s;
		  6'b101_111: sg_d <= h_g;
		  6'b011_111: sg_d <= h_s;
	  endcase 
	  end

 endmodule