Zynq的FPGA设计中[DRC 23-20]错误的解决

上次做DDS时出现了[DRC 23-20]，当时是这样处理的(并没有解决)：在网上搜了一下，新建一个tcl文件，在文件中添加

set_property SEVERITY {Warning} [get_drc_checks NSTD-1]

set_property SEVERITY {Warning} [get_drc_checks RTSTAT-1]

set_property SEVERITY {Warning} [get_drc_checks UCIO-1]

这几行语句，并在Project Settings中的Bitstream选项中添加新建的.tcl文本(tcl.pre栏)

怎么解决这个问题呢? 分析错误提示：

[DRC 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - 3 out of 3 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: clk, rst_n, LED.

再回到工程的xdc文件，发现确实还有几个接口没有添加约束。

综上：遇到[DRC 23-20]错误时，一般是没有将所有的输入输出端口进行约束好。