该专栏下文章为本人学习时的笔记及对一些知识点的理解,无法保证正确与否,有误之处还望指出。
程序:
module cfq(q,data,clk);
output q;
input data,clk;
reg q;
always@(posedge clk)
begin
q<=data;
end
endmodule
测试程序:
`timescale 1ns/1ns
module cfq_tb();
reg data,clk;
wire q;
cfq t1(
.q(q),
.data(data),
.clk(clk));
initial
begin
data = 0;
clk = 0;
#18 data = 1;
#16 data = 0;
end
always #5 clk <= ~clk;
endmodule
程序:
module scq1(q,data,clk);
output q;
input data,clk;
assign q=clk?data:q;
endmodule
测试程序:
`timescale 1ns/1ns
module scq1_tb();
reg data,clk;
wire q;
scq1 t1(
.q(q),
.data(data),
.clk(clk));
initial
begin
data = 0;
clk = 0;
#18 data = 1;
#16 data = 0;
end
always #5 clk <= ~clk;
endmodule
程序:
module scq2(q,data,clk,set,reset);
output q;
input data,clk,set,reset;
assign q=reset?0:(set?1:(clk?data:q));
endmodule
测试程序:
`timescale 1ns/1ns
module scq2_tb();
reg data,clk,set,reset;
wire q;
scq2 t1(
.q(q),
.data(data),
.clk(clk),
.set(set),
.reset(reset));
initial
begin
data = 1;
clk = 0;
set = 0;
reset = 0;
#18 data = 0;
#11 data = 1;
#8 data = 0;
#10 set=1;
#16 reset = 1;
end
always #5 clk <= ~clk;
endmodule
程序:
module ywjcq(din,clk,clr,dout);
input din,clk,clr;
output reg [7:0]dout;
always@(posedge clk)
begin
if(clr)
dout <= 8'b0;
else
begin
dout<=dout<<1;
dout[0]<=din;
end
end
endmodule
测试程序:
`timescale 1ns/1ns
module ywjcq_tb;
reg din,clk,clr;
wire [7:0]dout;
ywjcq t1(
.din(din),
.clk(clk),
.clr(clr),
.dout(dout));
initial
begin
clk = 0;
clr = 1;
#10 clr=0;
din = 1;
end
always #5 clk <= ~clk;
endmodule
程序:
module count8(out,cout,data,load,cin,clk);
output reg [7:0]out;
output cout;
input [7:0]data;
input load,cin,clk;
always@(posedge clk)
begin
if(load)
out <= data;
else
out <= out + cin;
end
assign cout=(&out)&cin;
endmodule
测试程序:
`timescale 1ns/1ns
module count8_tb();
reg load,cin,clk;
reg [7:0]data;
wire cout;
wire [7:0]out;
count8 t1(
.out(out),
.cout(cout),
.data(data),
.load(load),
.cin(cin),
.clk(clk));
initial
begin
clk = 0;
data = 8'b0;
load = 1;
cin = 1;
#10 load = 0;
end
always #5 clk <= ~clk;
endmodule