imx6q uboot nand flash支持

board/freescale/mx6qsabresd.c增加

#ifdef CONFIG_NAND_MXS

 
static iomux_v3_cfg_t gpmi_pads[] = {
MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0),
MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NANDF_CS1__NAND_CE1_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
//MX6_PAD_NANDF_CS2__NAND_CE2_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NANDF_CS3__NAND_CE3_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
/*MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL1),*/
};


static void setup_gpmi_nand(void)
{
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
unsigned int reg;


/* config gpio iomux */
imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
/*set eim_pads */
imx_iomux_v3_setup_multiple_pads(fpga_eim_pads, ARRAY_SIZE(fpga_eim_pads));


/* config gpmi nand iomux */
imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));


/*setup_gpmi_io_clk((MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)));*/


/* config gpmi and bch clock to 20Mhz, from pll2 400M pfd*/
reg = readl(CCM_BASE_ADDR + 0x2c);
reg &= 0xF800FFFF;
reg |= 0x02630000;
writel(reg, CCM_BASE_ADDR + 0x2c);


/* enable gpmi and bch clock gating */
reg = readl(CCM_BASE_ADDR + 0x78);
reg |= 0xFF003000;
writel(reg, CCM_BASE_ADDR + 0x78);


/* enable apbh clock gating */
reg = readl(CCM_BASE_ADDR + 0x68);
reg |= 0x0030;
writel(reg, CCM_BASE_ADDR + 0x68);


/* enable apbh clock gating */
/*setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);*/
}

#endif

board_init()函数中增加

#ifdef CONFIG_NAND_MXS 
setup_gpmi_nand();
#endif