通信 - Verilog实现相关捕获（帧同步）代码

帧同步的相关捕获。在matlab上实现相关捕获的仿真只需要几行相乘相加就可以，但是硬件实现时候确是比较复杂的，尤其是需要不停进行移位相乘相加，手动写这个代码，那Ctrl+C + Ctrl+V到心碎，还容易出错。今天突发奇想，采用C/C++语言通过写文件的方式来编写相关捕获的Verilog代码，进行了一下仿真，功能仿真（前仿）正确。这里，记录一波骚操作。

// 用于实现相关捕获的verilog代码
// 2019-05-19

#include 
#include 

using namespace std;

#define		LEN		512

void module_declaration(FILE* fp);
void variable_declaration(FILE* fp);
void shift_register(FILE* fp);
void multi_mSeq_local(FILE* fp);
void addr_reg_module0(FILE* fp);
void addr_reg1_1st(FILE* fp);
void addr_reg2_2nd(FILE* fp);
void addr_reg3_3rd(FILE* fp);
void addr_reg4_4th(FILE* fp);
void addr_reg5_5th(FILE* fp);
void addr_reg6_6th(FILE* fp);
void addr_reg7_7th(FILE* fp);
void addr_reg8_8th(FILE* fp);
void addr_reg9_9th(FILE* fp);
void module_end(FILE* fp);


int main()
{
	FILE* fp = fopen("Shift_Register.v", "w");

	module_declaration(fp);
	variable_declaration(fp);
	//init_mSeq(fp);
	shift_register(fp);
	multi_mSeq_local(fp);
	addr_reg1_1st(fp);
	addr_reg2_2nd(fp);
	addr_reg3_3rd(fp);
	addr_reg4_4th(fp);
	addr_reg5_5th(fp);
	addr_reg6_6th(fp);
	addr_reg7_7th(fp);
	addr_reg8_8th(fp);
	addr_reg9_9th(fp);
	module_end(fp);

	fclose(fp);

	return 0;
}

// 模块声明
void module_declaration(FILE* fp)
{
	if (fp){
		time_t	curTime = time(NULL);
		struct tm* sysTime = localtime(&curTime);
		fprintf(fp, "// %d-%02d-%02d %02d:%02d:%02d \n\n\n", sysTime->tm_year + 1900, sysTime->tm_mon + 1, sysTime->tm_mday, sysTime->tm_hour, sysTime->tm_min, sysTime->tm_sec);

		fprintf(fp, "module Shift_Register(\n");
		fprintf(fp, "							clk,\n");
		fprintf(fp, "							reset,\n");
		fprintf(fp, "							data_in,\n");
		fprintf(fp, "							relate_peak\n");
		fprintf(fp, "						);\n\n");

		fprintf(fp, "input	wire				clk, reset;\n");
		fprintf(fp, "input	wire[11 : 0]		data_in;\n");
		fprintf(fp, "output	reg	[20 : 0]		relate_peak;\n\n\n");
	}
}


//变量声明
void variable_declaration(FILE* fp)
{
	if (fp){
		fprintf(fp, "reg	signed	[ 1 : 0]		m[511 : 0];\n");
		fprintf(fp, "reg	signed	[11 : 0]		shift_reg[511 : 0];\n\n\n");

		fprintf(fp, "reg	signed	[11 : 0]		adder_reg0[511 : 0];\n");
		fprintf(fp, "reg	signed	[12 : 0]		adder_reg1[255 : 0];\n");
		fprintf(fp, "reg	signed	[13 : 0]		adder_reg2[127 : 0];\n");
		fprintf(fp, "reg	signed	[14 : 0]		adder_reg3[63 : 0];\n");
		fprintf(fp, "reg	signed	[15 : 0]		adder_reg4[31 : 0];\n");
		fprintf(fp, "reg	signed	[16 : 0]		adder_reg5[15 : 0];\n");
		fprintf(fp, "reg	signed	[17 : 0]		adder_reg6[7 : 0];\n");
		fprintf(fp, "reg	signed	[18 : 0]		adder_reg7[3 : 0];\n");
		fprintf(fp, "reg	signed	[19 : 0]		adder_reg8[1 : 0];\n");
		//fprintf(fp, "%s\n", "reg	signed	[20 : 0]		adder_reg9;");
		fprintf(fp, "\n\n\n");
	}
}

// 移位操作
void shift_register(FILE* fp)
{
	if (fp){
		fprintf(fp, "always@(posedge clk, negedge reset)\n");
		fprintf(fp, "begin\n");
		fprintf(fp, "	if(!reset)\n");
		fprintf(fp, "	begin\n");
		for (int i = 0; i < LEN; i++){	
			fprintf(fp, "		shift_reg[%d]		<=	12'd0;\n", i);
		}
		fprintf(fp, "	end\n");
		fprintf(fp, "	else\n");
		fprintf(fp, "	begin\n");
		for (int i = 1; i < LEN; i++){
			fprintf(fp, "		shift_reg[%d]		<=	shift_reg[%d];\n", i - 1, i);
		}
		fprintf(fp, "		shift_reg[%d]		<=	data_in;\n", LEN - 1);
		fprintf(fp, "	end\n");
		fprintf(fp, "end\n\n\n\n");
	}
}

// 与本地m序列相乘
void multi_mSeq_local(FILE* fp)
{
	FILE* fm = fopen("m_Seq.txt", "r");
	if (fp && fm){
		fprintf(fp, "wire	signed	[11 : 0]	mult_result[511 : 0];\n\n");

		fprintf(fp, "always@(posedge clk, negedge reset)\n");
		fprintf(fp, "begin\n");
		fprintf(fp, "	if(!reset)\n");
		fprintf(fp, "	begin\n");
		char str[4];
		for (int i = 0; i < LEN; i++){
			fgets(str, 4, fm);
			fprintf(fp, "		m[%d]		<=	2'b%c%c;\n", i, str[0], str[1]);
		}
		fprintf(fp, "	end\n");
		fprintf(fp, "	else\n");
		fprintf(fp, "	begin\n");
		for (int i = 0; i < LEN; i++){
			fprintf(fp, "		adder_reg0[%d]		<=	mult_result[%d];\n", i, i);
		}
		fprintf(fp, "	end\n");
		fprintf(fp, "end\n\n\n\n");

	}
}

void addr_reg1_1st(FILE* fp)
{
	if (fp){
		fprintf(fp, "always@(posedge clk, negedge reset)\n");
		fprintf(fp, "begin\n");
		fprintf(fp, "	if(!reset)\n");
		fprintf(fp, "	begin\n");
		for (int i = 0; i < LEN / 2; i++){
			fprintf(fp, "		adder_reg1[%d]		<=	13'd0;\n", i);
		}
		fprintf(fp, "	end\n");
		fprintf(fp, "	else\n");
		fprintf(fp, "	begin\n");
		for (int i = 0; i < LEN / 2; i++){
			fprintf(fp, "		adder_reg1[%d]		<=	adder_reg0[%d]	+	adder_reg0[%d];\n", i, 2 * i, 2 * i + 1);
		}
		fprintf(fp, "	end\n");
		fprintf(fp, "end\n\n\n\n");
	}
}

void addr_reg2_2nd(FILE* fp)
{
	if (fp){
		fprintf(fp, "always@(posedge clk, negedge reset)\n");
		fprintf(fp, "begin\n");
		fprintf(fp, "	if(!reset)\n");
		fprintf(fp, "	begin\n");
		for (int i = 0; i < LEN / 4; i++){
			fprintf(fp, "		adder_reg2[%d]		<=	14'd0;\n", i);
		}
		fprintf(fp, "	end\n");
		fprintf(fp, "	else\n");
		fprintf(fp, "	begin\n");
		for (int i = 0; i < LEN / 4; i++){
			fprintf(fp, "		adder_reg2[%d]		<=	adder_reg1[%d]	+	adder_reg1[%d];\n", i, 2 * i, 2 * i + 1);
		}
		fprintf(fp, "	end\n");
		fprintf(fp, "end\n\n\n\n");
	}
}

void addr_reg3_3rd(FILE* fp)
{
	if (fp){
		fprintf(fp, "always@(posedge clk, negedge reset)\n");
		fprintf(fp, "begin\n");
		fprintf(fp, "	if(!reset)\n");
		fprintf(fp, "	begin\n");
		for (int i = 0; i < LEN / 8; i++){
			fprintf(fp, "		adder_reg3[%d]		<=	15'd0;\n", i);
		}
		fprintf(fp, "	end\n");
		fprintf(fp, "	else\n");
		fprintf(fp, "	begin\n");
		for (int i = 0; i < LEN / 8; i++){
			fprintf(fp, "		adder_reg3[%d]		<=	adder_reg2[%d]	+	adder_reg2[%d];\n", i, 2 * i, 2 * i + 1);
		}
		fprintf(fp, "	end\n");
		fprintf(fp, "end\n\n\n\n");
	}
}

void addr_reg4_4th(FILE* fp)
{
	if (fp){
		fprintf(fp, "always@(posedge clk, negedge reset)\n");
		fprintf(fp, "begin\n");
		fprintf(fp, "	if(!reset)\n");
		fprintf(fp, "	begin\n");
		for (int i = 0; i < LEN / 16; i++){
			fprintf(fp, "		adder_reg4[%d]		<=	16'd0;\n", i);
		}
		fprintf(fp, "	end\n");
		fprintf(fp, "	else\n");
		fprintf(fp, "	begin\n");
		for (int i = 0; i < LEN / 16; i++){
			fprintf(fp, "		adder_reg4[%d]		<=	adder_reg3[%d]	+	adder_reg3[%d];\n", i, 2 * i, 2 * i + 1);
		}
		fprintf(fp, "	end\n");
		fprintf(fp, "end\n\n\n\n");
	}
}

void addr_reg5_5th(FILE* fp)
{
	if (fp){
		fprintf(fp, "always@(posedge clk, negedge reset)\n");
		fprintf(fp, "begin\n");
		fprintf(fp, "	if(!reset)\n");
		fprintf(fp, "	begin\n");
		for (int i = 0; i < LEN / 32; i++){
			fprintf(fp, "		adder_reg5[%d]		<=	17'd0;\n", i);
		}
		fprintf(fp, "	end");
		fprintf(fp, "	else");
		fprintf(fp, "	begin");
		for (int i = 0; i < LEN / 32; i++){
			fprintf(fp, "		adder_reg5[%d]		<=	adder_reg4[%d]	+	adder_reg4[%d];\n", i, 2 * i, 2 * i + 1);
		}
		fprintf(fp, "	end\n");
		fprintf(fp, "end\n\n\n\n");
	}
}

void addr_reg6_6th(FILE* fp)
{
	if (fp){
		fprintf(fp, "always@(posedge clk, negedge reset)\n");
		fprintf(fp, "begin\n");
		fprintf(fp, "	if(!reset)\n");
		fprintf(fp, "	begin\n");
		for (int i = 0; i < LEN / 64; i++){
			fprintf(fp, "		adder_reg6[%d]		<=	18'd0;\n", i);
		}
		fprintf(fp, "	end\n");
		fprintf(fp, "	else\n");
		fprintf(fp, "	begin\n");
		for (int i = 0; i < LEN / 64; i++){
			fprintf(fp, "		adder_reg6[%d]		<=	adder_reg5[%d]	+	adder_reg5[%d];\n", i, 2 * i, 2 * i + 1);
		}
		fprintf(fp, "	end\n");
		fprintf(fp, "end\n\n\n\n");
	}
}

void addr_reg7_7th(FILE* fp)
{
	if (fp){
		fprintf(fp, "always@(posedge clk, negedge reset)\n");
		fprintf(fp, "begin\n");
		fprintf(fp, "	if(!reset)\n");
		fprintf(fp, "	begin\n");
		for (int i = 0; i < LEN / 128; i++){
			fprintf(fp, "		adder_reg7[%d]		<=	19'd0;\n", i);
		}
		fprintf(fp, "	end\n");
		fprintf(fp, "	else\n");
		fprintf(fp, "	begin\n");
		for (int i = 0; i < LEN / 128; i++){
			fprintf(fp, "		adder_reg7[%d]		<=	adder_reg6[%d]	+	adder_reg6[%d];\n", i, 2 * i, 2 * i + 1);
		}
		fprintf(fp, "	end\n");
		fprintf(fp, "end\n\n\n\n");
	}
}

void addr_reg8_8th(FILE* fp)
{
	if (fp){
		fprintf(fp, "always@(posedge clk, negedge reset)\n");
		fprintf(fp, "begin\n");
		fprintf(fp, "	if(!reset)\n");
		fprintf(fp, "	begin\n");
		for (int i = 0; i < LEN / 256; i++){
			fprintf(fp, "		adder_reg8[%d]		<=	20'd0;\n", i);
		}
		fprintf(fp, "	end\n");
		fprintf(fp, "	else\n");
		fprintf(fp, "	begin\n");
		for (int i = 0; i < LEN / 256; i++){
			fprintf(fp, "		adder_reg8[%d]		<=	adder_reg7[%d]	+	adder_reg7[%d];\n", i, 2 * i, 2 * i + 1);
		}
		fprintf(fp, "	end\n");
		fprintf(fp, "end\n\n\n\n");
	}
}

void addr_reg9_9th(FILE* fp)
{
	if (fp){
		fprintf(fp, "always@(posedge clk, negedge reset)\n");
		fprintf(fp, "begin\n");
		fprintf(fp, "	if(!reset)\n");
		fprintf(fp, "	begin\n");
		for (int i = 0; i < LEN / 512; i++){
			fprintf(fp, "		relate_peak			<= 	21'd0;");
		}
		fprintf(fp, "	end\n");
		fprintf(fp, "	else\n");
		fprintf(fp, "	begin\n");
		for (int i = 0; i < LEN / 512; i++){
			fprintf(fp, "		relate_peak			<=	adder_reg8[%d]	+	adder_reg8[%d];\n", 2 * i, 2 * i + 1);
		}
		fprintf(fp, "	end\n");
		fprintf(fp, "end\n\n\n\n");
	}
}

// 模块结束
void module_end(FILE* fp)
{
	if (fp){
		for (int i = 0; i < LEN; i++){
			fprintf(fp, "assign mult_result[%d] = (m[%d][1]	!=	shift_reg[%d][11])	?	~shift_reg[%d]	+	12'd1 : (m[%d][1] == 2'd1)	?	~shift_reg[%d]	+	12'd1	:	shift_reg[%d];\n", i, i, i, i, i, i, i);
		}
		fprintf(fp, "\n\n\n\n");
		fprintf(fp, "endmodule\n\n");
	}
}