参考设计，实现简单的AXI-M接口的DMA功能
`timescale 1 ns / 1 ps
module myip_v3_M00_AXI #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Base address of targeted slave
parameter C_M_TARGET_SLAVE_BASE_ADDR = 32'h40000000,
// Burst Length. Supports 1, 2, 4, 8, 16, 32, 64, 128, 256 burst lengths
parameter integer C_M_AXI_BURST_LEN = 16,
// Thread ID Width
parameter integer C_M_AXI_ID_WIDTH = 1,
// Width of Address Bus
parameter integer C_M_AXI_ADDR_WIDTH = 32,
// Width of Data Bus
parameter integer C_M_AXI_DATA_WIDTH = 32,
// Width of User Write Address Bus
parameter integer C_M_AXI_AWUSER_WIDTH = 0,
// Width of User Read Address Bus
parameter integer C_M_AXI_ARUSER_WIDTH = 0,
// Width of User Write Data Bus
parameter integer C_M_AXI_WUSER_WIDTH = 0,
// Width of User Read Data Bus
parameter integer C_M_AXI_RUSER_WIDTH = 0,
// Width of User Response Bus
parameter integer C_M_AXI_BUSER_WIDTH = 0
)
(
// Users to add ports here
// User ports ends
// Do not modify the ports beyond this line
// Global Clock Signal.
input wire M_AXI_ACLK,
// Global Reset Singal. This Signal is Active Low
input wire M_AXI_ARESETN,
// Master Interface Write Address ID
output wire [C_M_AXI_ID_WIDTH-1 : 0] M_AXI_AWID,
// Master Interface Write Address
output wire [C_M_AXI_ADDR_WIDTH-1 : 0] M_AXI_AWADDR,
// Burst length. The burst length gives the exact number of transfers in a burst
output wire [7 : 0] M_AXI_AWLEN,
// Burst size. This signal indicates the size of each transfer in the burst
output wire [2 : 0] M_AXI_AWSIZE,
// Burst type. The burst type and the size information,
// determine how the address for each transfer within the burst is calculated.
output wire [1 : 0] M_AXI_AWBURST,
// Lock type. Provides additional information about the
// atomic characteristics of the transfer.
output wire M_AXI_AWLOCK,
// Memory type. This signal indicates how transactions
// are required to progress through a system.
output wire [3 : 0] M_AXI_AWCACHE,
// Protection type. This signal indicates the privilege
// and security level of the transaction, and whether
// the transaction is a data access or an instruction access.
output wire [2 : 0] M_AXI_AWPROT,
// Quality of Service, QoS identifier sent for each write transaction.
output wire [3 : 0] M_AXI_AWQOS,
// Optional User-defined signal in the write address channel.
output wire [C_M_AXI_AWUSER_WIDTH-1 : 0] M_AXI_AWUSER,
// Write address valid. This signal indicates that
// the channel is signaling valid write address and control information.
output wire M_AXI_AWVALID,
// Write address ready. This signal indicates that
// the slave is ready to accept an address and associated control signals
input wire M_AXI_AWREADY,
// Master Interface Write Data.
output wire [C_M_AXI_DATA_WIDTH-1 : 0] M_AXI_WDATA,
// Write strobes. This signal indicates which byte
// lanes hold valid data. There is one write strobe
// bit for each eight bits of the write data bus.
output wire [C_M_AXI_DATA_WIDTH/8-1 : 0] M_AXI_WSTRB,
// Write last. This signal indicates the last transfer in a write burst.
output wire M_AXI_WLAST,
// Optional User-defined signal in the write data channel.
output wire [C_M_AXI_WUSER_WIDTH-1 : 0] M_AXI_WUSER,
// Write valid. This signal indicates that valid write
// data and strobes are available
output wire M_AXI_WVALID,
// Write ready. This signal indicates that the slave
// can accept the write data.
input wire M_AXI_WREADY,
// Master Interface Write Response.
input wire [C_M_AXI_ID_WIDTH-1 : 0] M_AXI_BID,
// Write response. This signal indicates the status of the write transaction.
input wire [1 : 0] M_AXI_BRESP,
// Optional User-defined signal in the write response channel
input wire [C_M_AXI_BUSER_WIDTH-1 : 0] M_AXI_BUSER,
// Write response valid. This signal indicates that the
// channel is signaling a valid write response.
input wire M_AXI_BVALID,
// Response ready. This signal indicates that the master
// can accept a write response.
output wire M_AXI_BREADY,
// Master Interface Read Address.
output wire [C_M_AXI_ID_WIDTH-1 : 0] M_AXI_ARID,
// Read address. This signal indicates the initial
// address of a read burst transaction.
output wire [C_M_AXI_ADDR_WIDTH-1 : 0] M_AXI_ARADDR,
// Burst length. The burst length gives the exact number of transfers in a burst
output wire [7 : 0] M_AXI_ARLEN,
// Burst size. This signal indicates the size of each transfer in the burst
output wire [2 : 0] M_AXI_ARSIZE,
// Burst type. The burst type and the size information,
// determine how the address for each transfer within the burst is calculated.
output wire [1 : 0] M_AXI_ARBURST,
// Lock type. Provides additional information about the
// atomic characteristics of the transfer.
output wire M_AXI_ARLOCK,
// Memory type. This signal indicates how transactions
// are required to progress through a system.
output wire [3 : 0] M_AXI_ARCACHE,
// Protection type. This signal indicates the privilege
// and security level of the transaction, and whether
// the transaction is a data access or an instruction access.
output wire [2 : 0] M_AXI_ARPROT,
// Quality of Service, QoS identifier sent for each read transaction
output wire [3 : 0] M_AXI_ARQOS,
// Optional User-defined signal in the read address channel.
output wire [C_M_AXI_ARUSER_WIDTH-1 : 0] M_AXI_ARUSER,
// Write address valid. This signal indicates that
// the channel is signaling valid read address and control information
output wire M_AXI_ARVALID,
// Read address ready. This signal indicates that
// the slave is ready to accept an address and associated control signals
input wire M_AXI_ARREADY,
// Read ID tag. This signal is the identification tag
// for the read data group of signals generated by the slave.
input wire [C_M_AXI_ID_WIDTH-1 : 0] M_AXI_RID,
// Master Read Data
input wire [C_M_AXI_DATA_WIDTH-1 : 0] M_AXI_RDATA,
// Read response. This signal indicates the status of the read transfer
input wire [1 : 0] M_AXI_RRESP,
// Read last. This signal indicates the last transfer in a read burst
input wire M_AXI_RLAST,
// Optional User-defined signal in the read address channel.
input wire [C_M_AXI_RUSER_WIDTH-1 : 0] M_AXI_RUSER,
// Read valid. This signal indicates that the channel
// is signaling the required read data.
input wire M_AXI_RVALID,
// Read ready. This signal indicates that the master can
// accept the read data and response information.
output wire M_AXI_RREADY,
//data_if
input [71:0] dma_data,
input dma_den,
output dma_ready,
output [71:0] cpld_data,
output cpld_en
);
////////////////////////////////////////////
// define
////////////////////////////////////////////
// rx data buf
reg dma_ready_r;
wire axim_buf_ren;
wire [71:0] axim_buf_dout;
wire axim_buf_empty;
wire [9:0] axim_buf_count;
// main control FSM
reg [2:0] fsm_axim;
// F_IDLE
wire axim_buf_ren_idle;
reg [31:0] axim_address;
reg [10:0] axim_bytecount_sub1;
wire [7:0] axim_length;
wire [2:0] axim_byte_mod;
reg [1:0] axim_cpld_port;
// F_WR_ADRS
// F_WR_DATA
wire axim_buf_ren_wrdata;
reg [7:0] axim_wrdata_cnt;
// F_WR_END
// F_RD_ADRS
// F_RD_DATA
// cpld interface
reg [71:0] cpld_data_r;
reg cpld_en_r;
////////////////////////////////////////////
// rx data buf
////////////////////////////////////////////
always @(posedge M_AXI_ACLK)begin
dma_ready_r <= (axim_buf_count[9:8]>=2'b01) ? 1'b0 : 1'b1;
end
assign dma_ready = dma_ready_r;
fifo_ccbram_72w512d axim_data_buf(
.clk (M_AXI_ACLK),
.srst (~M_AXI_ARESETN),
.din (dma_data),
.wr_en (dma_den),
.rd_en (axim_buf_ren),
.dout (axim_buf_dout),
.full (),
.empty (axim_buf_empty),
.data_count (axim_buf_count)
);
assign axim_buf_ren = axim_buf_ren_idle | axim_buf_ren_wrdata;
////////////////////////////////////////////
// main control FSM
////////////////////////////////////////////
parameter F_IDLE = 3'h0;
parameter F_WR_ADRS = 3'h1;
parameter F_WR_DATA = 3'h2;
parameter F_WR_END = 3'h3;
parameter F_RD_ADRS = 3'h4;
parameter F_RD_DATA = 3'h5;
always @(posedge M_AXI_ACLK)begin
if(M_AXI_ARESETN==1'b0)begin
fsm_axim <= F_IDLE;
end else begin
case(fsm_axim)
F_IDLE : if(axim_buf_empty==1'b0 && axim_buf_dout[71:70]==2'b10)begin
fsm_axim <= F_WR_ADRS;
end else if(axim_buf_empty==1'b0 && axim_buf_dout[71:70]==2'b11)begin
fsm_axim <= F_RD_ADRS;
end
F_WR_ADRS : if(M_AXI_AWVALID & M_AXI_AWREADY)begin
fsm_axim <= F_WR_DATA;
end
F_WR_DATA : if(M_AXI_WLAST & M_AXI_WVALID & M_AXI_WREADY)begin
fsm_axim <= F_WR_END;
end
F_WR_END : if(M_AXI_BVALID & M_AXI_BREADY)begin
fsm_axim <= F_IDLE;
end
F_RD_ADRS : if(M_AXI_ARVALID & M_AXI_ARREADY)begin
fsm_axim <= F_RD_DATA;
end
F_RD_DATA : if(M_AXI_RLAST & M_AXI_RVALID & M_AXI_RREADY)begin
fsm_axim <= F_IDLE;
end
default : fsm_axim <= F_IDLE;
endcase
end
end
////////////////////////////////////////////
// F_IDLE
////////////////////////////////////////////
assign axim_buf_ren_idle = (fsm_axim==F_IDLE) && (axim_buf_empty==1'b0);
always @(posedge M_AXI_ACLK)begin
if(axim_buf_ren_idle)begin
axim_address <= axim_buf_dout[31:0];
axim_bytecount_sub1 <= axim_buf_dout[42:32]-1'b1;
axim_cpld_port <= axim_buf_dout[69:68];
end
end
assign axim_length = axim_bytecount_sub1[10:3]; //0~255:act 1~256
assign axim_byte_mod = axim_bytecount_sub1[2:0]; //0~7:act 1~all
////////////////////////////////////////////
// F_WR_ADRS
////////////////////////////////////////////
assign M_AXI_AWID ='b0;
assign M_AXI_AWADDR = axim_address;
assign M_AXI_AWLEN = axim_length;
assign M_AXI_AWSIZE = 3'h3;
assign M_AXI_AWBURST = 2'b01;
assign M_AXI_AWLOCK = 1'b0;
assign M_AXI_AWCACHE = 4'b0010;
assign M_AXI_AWPROT = 3'h0;
assign M_AXI_AWQOS = 4'h0;
assign M_AXI_AWUSER = 'b1;
assign M_AXI_AWVALID = (fsm_axim==F_WR_ADRS);
////////////////////////////////////////////
// F_WR_DATA
////////////////////////////////////////////
assign axim_buf_ren_wrdata = M_AXI_WVALID & M_AXI_WREADY & (axim_buf_empty==1'b0);
assign M_AXI_WDATA = axim_buf_dout[63:0];
assign M_AXI_WSTRB = 8'hff;
assign M_AXI_WLAST = (axim_wrdata_cnt==axim_length);
assign M_AXI_WUSER = 'b0;
assign M_AXI_WVALID = (fsm_axim==F_WR_DATA && axim_buf_empty==1'b0);
always @(posedge M_AXI_ACLK)begin
if(fsm_axim==F_WR_DATA)begin
if(axim_buf_ren_wrdata)begin
axim_wrdata_cnt <= axim_wrdata_cnt + 1'b1;
end
end else begin
axim_wrdata_cnt <= 8'b0;
end
end
////////////////////////////////////////////
// F_WR_END
////////////////////////////////////////////
assign M_AXI_BREADY = 1'b1;
////////////////////////////////////////////
// F_RD_ADRS
////////////////////////////////////////////
assign M_AXI_ARID = 'b0;
assign M_AXI_ARADDR = axim_address;
assign M_AXI_ARLEN = axim_length;
assign M_AXI_ARSIZE = 3'h3;
assign M_AXI_ARBURST = 2'b01;
assign M_AXI_ARLOCK = 1'b0;
assign M_AXI_ARCACHE = 4'b0010;
assign M_AXI_ARPROT = 3'h0;
assign M_AXI_ARQOS = 4'h0;
assign M_AXI_ARUSER = 'b1;
assign M_AXI_ARVALID = (fsm_axim==F_RD_ADRS);
////////////////////////////////////////////
// F_RD_DATA
////////////////////////////////////////////
assign M_AXI_RREADY = 1'b1;
////////////////////////////////////////////
// cpld interface
////////////////////////////////////////////
always @(posedge M_AXI_ACLK)begin
cpld_data_r[71] <= 1'b0; //unused
cpld_data_r[70] <= M_AXI_RVALID & M_AXI_RREADY & M_AXI_RLAST;
cpld_data_r[69:68] <= axim_cpld_port;
cpld_data_r[67] <= 1'b0;
cpld_data_r[66:64] <= axim_byte_mod;
cpld_data_r[63:00] <= M_AXI_RDATA;
cpld_en_r <= M_AXI_RVALID & M_AXI_RREADY;
end
assign cpld_data = cpld_data_r;
assign cpld_en = cpld_en_r;
endmodule
//`define eeprom_on
`timescale 1 ns / 1 ps
module myip_v3_S01_AXI #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Width of S_AXI data bus
parameter integer C_S_AXI_DATA_WIDTH = 32,
// Width of S_AXI address bus
parameter integer C_S_AXI_ADDR_WIDTH = 4
)
(
// Users to add ports here
// User ports ends
// Do not modify the ports beyond this line
// Global Clock Signal
input wire S_AXI_ACLK,
// Global Reset Signal. This Signal is Active LOW
input wire S_AXI_ARESETN,
// Write address (issued by master, acceped by Slave)
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
// Write channel Protection type. This signal indicates the
// privilege and security level of the transaction, and whether
// the transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_AWPROT,
// Write address valid. This signal indicates that the master signaling
// valid write address and control information.
input wire S_AXI_AWVALID,
// Write address ready. This signal indicates that the slave is ready
// to accept an address and associated control signals.
output wire S_AXI_AWREADY,
// Write data (issued by master, acceped by Slave)
input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
// Write strobes. This signal indicates which byte lanes hold
// valid data. There is one write strobe bit for each eight
// bits of the write data bus.
input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
// Write valid. This signal indicates that valid write
// data and strobes are available.
input wire S_AXI_WVALID,
// Write ready. This signal indicates that the slave
// can accept the write data.
output wire S_AXI_WREADY,
// Write response. This signal indicates the status
// of the write transaction.
output wire [1 : 0] S_AXI_BRESP,
// Write response valid. This signal indicates that the channel
// is signaling a valid write response.
output wire S_AXI_BVALID,
// Response ready. This signal indicates that the master
// can accept a write response.
input wire S_AXI_BREADY,
// Read address (issued by master, acceped by Slave)
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
// Protection type. This signal indicates the privilege
// and security level of the transaction, and whether the
// transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_ARPROT,
// Read address valid. This signal indicates that the channel
// is signaling valid read address and control information.
input wire S_AXI_ARVALID,
// Read address ready. This signal indicates that the slave is
// ready to accept an address and associated control signals.
output wire S_AXI_ARREADY,
// Read data (issued by slave)
output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
// Read response. This signal indicates the status of the
// read transfer.
output wire [1 : 0] S_AXI_RRESP,
// Read valid. This signal indicates that the channel is
// signaling the required read data.
output wire S_AXI_RVALID,
// Read ready. This signal indicates that the master can
// accept the read data and response information.
input wire S_AXI_RREADY,
//hostreg
output reg oline0_en,
output reg [19:0] oline0_data_baseadrs,
output reg [19:0] oline0_mesg_baseadrs,
output reg [19:0] oline0_fpgawr_point_baseadrs,
output reg [01:0] oline0_depth_define,
output reg [07:0] oline0_mesg_toutcfg,
output reg [09:0] oline0_cpu_point,
input [09:0] iline0_fpga_point,
output reg oline1_en,
output reg [19:0] oline1_data_baseadrs,
output reg [19:0] oline1_mesg_baseadrs,
output reg [19:0] oline1_fpgawr_point_baseadrs,
output reg [01:0] oline1_depth_define,
output reg [07:0] oline1_mesg_toutcfg,
output reg [09:0] oline1_cpu_point,
input [09:0] iline1_fpga_point,
output reg oline2_en,
output reg [19:0] oline2_data_baseadrs,
output reg [19:0] oline2_mesg_baseadrs,
output reg [19:0] oline2_fpgawr_point_baseadrs,
output reg [01:0] oline2_depth_define,
output reg [07:0] oline2_mesg_toutcfg,
output reg [09:0] oline2_cpu_point,
input [09:0] iline2_fpga_point,
output reg oline3_en,
output reg [19:0] oline3_data_baseadrs,
output reg [19:0] oline3_mesg_baseadrs,
output reg [19:0] oline3_fpgawr_point_baseadrs,
output reg [01:0] oline3_depth_define,
output reg [07:0] oline3_mesg_toutcfg,
output reg [09:0] oline3_cpu_point,
input [09:0] iline3_fpga_point,
output reg oline4_en,
output reg [19:0] oline4_data_baseadrs,
output reg [19:0] oline4_mesg_baseadrs,
output reg [19:0] oline4_fpgawr_point_baseadrs,
output reg [01:0] oline4_depth_define,
output reg [07:0] oline4_mesg_toutcfg,
output reg [09:0] oline4_cpu_point,
input [09:0] iline4_fpga_point,
//mac-0/1
output olbus_req_p0,
output olbus_req_p1,
output olbus_req_p2,
output olbus_req_p3,
output olbus_rw,
output [15:0] olbus_addr,
output [31:0] olbus_wdata,
input ilbus_ack_p0,
input ilbus_ack_p1,
input ilbus_ack_p2,
input ilbus_ack_p3,
input [31:0] ilbus_rdata_p0,
input [31:0] ilbus_rdata_p1,
input [31:0] ilbus_rdata_p2,
input [31:0] ilbus_rdata_p3,
//GPIO-bank34
input PCB_ID0,
input PCB_ID1,
input PCB_ID2,
//GPIO-bank35
input DEBUG_TEST ,
inout EEPORM_SDA ,
output EEPROM_CLK ,
output reg EEPROM_WP ,
output reg eMMC_RST ,
output reg FAN_OPEN ,
input PHY_DEBUG_INT ,
input PHY_PORT0_INT ,
input PHY_PORT0_LED2 ,
output reg PHY_PORT0_RST ,
input PHY_PORT1_INT ,
input PHY_PORT1_LED2 ,
output reg PHY_PORT1_RST ,
output reg RUN_LED_G ,
output reg RUN_LED_R ,
output reg USB_LED_G ,
output reg USB_LED_R ,
input sys_clk,
input [31:0] dma_pulse,
input [31:0] dma_state,
input [7:0] bridge_host2sw_pulse,
input [5:0] bridge_sw2host_pulse,
input [31:0] iready_other_state,
input [2:0] host_eth_user_pls,
input [2:0] sw_eth_user_pls,
output reg [47:0] arm_mac,
output reg [1:0] DFT_mode,
output reg eth_host_sys_loop,
output reg eth_sw_sys_loop,
output reg eth_host_line_loop,
output reg eth_sw_line_loop,
output reg host_selftest_flag,
input [7:0] host_self_check_err,
output reg sw_selftest_flag,
input [7:0] sw_self_check_err,
input [11:0] table3_cnt_inused,
input [11:0] table3_cnt_pushout,
input [11:0] table5_cnt_inused,
input [11:0] table5_cnt_pushout
);
// AXI4LITE signals
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_addr;
reg [C_S_AXI_DATA_WIDTH-1 : 0] axi_wdata;
reg axi_rw;
reg axi_awready;
reg axi_wready;
//reg [1 : 0] axi_bresp;
reg axi_bvalid;
//reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_araddr;
reg axi_arready;
reg [C_S_AXI_DATA_WIDTH-1 : 0] axi_rdata;
//reg [1 : 0] axi_rresp;
reg axi_rvalid;
// Example-specific design signals
// local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
// ADDR_LSB is used for addressing 32/64 bit registers/memories
// ADDR_LSB = 2 for 32 bits (n downto 2)
// ADDR_LSB = 3 for 64 bits (n downto 3)
localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1;
localparam integer OPT_MEM_ADDR_BITS = 1;
//----------------------------------------------
//-- Signals for user logic register space example
//------------------------------------------------
//-- Number of Slave Registers 4
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg0;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg1;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg2;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg3;
reg slv_reg_rden;
reg slv_reg_wren;
reg slv_reg_wren_magic;
reg [C_S_AXI_DATA_WIDTH-1:0] reg_data_out_00xx;
reg [C_S_AXI_DATA_WIDTH-1:0] reg_data_out_01xx;
integer byte_index;
reg aw_en;
reg axi_req_p0;
reg axi_req_p1;
reg axi_req_p2;
reg axi_req_p3;
//eeprom
`ifdef eeprom_on
reg i2c_opt_en;
reg i2c_opt_wr;
reg [15:0] i2c_addr;
reg [15:0] i2c_wrdata;
wire [15:0] i2c_rddata;
reg i2c_opt_en_r1;
reg i2c_opt_en_r2;
reg i2c_wr;
reg i2c_rd;
reg i2c_rdy_load;
wire i2c_rdy;
wire [31:0] fsm_sft;
`endif
//gpio
reg [15:0] test_reg;
reg cnt_clr;
//xadc
reg [6:0] xadc_daddr_in;
reg [3:0] den_cnt;
reg den_pls;
wire drdy_out;
wire [15:0] do_out;
reg [16:0] do_out_load;
//debug cnt==========
reg [21*8+7:0] dma_pulse_cnt='b0;
generate
genvar i;
for(i=0;i<=21;i=i+1)begin
always @ (posedge sys_clk)begin
if(cnt_clr)begin
dma_pulse_cnt[i*8+7:i*8] <= 8'b0;
end else if(dma_pulse[i])begin
dma_pulse_cnt[i*8+7:i*8] <= dma_pulse_cnt[i*8+7:i*8] + 1'b1;
end
end
end
endgenerate
reg [7*8+7:0] bridge_host2sw_pulse_cnt='b0;
generate
genvar j;
for(j=0;j<=7;j=j+1)begin
always @ (posedge sys_clk)begin
if(cnt_clr)begin
bridge_host2sw_pulse_cnt[j*8+7:j*8] <= 8'b0;
end else if(bridge_host2sw_pulse[j])begin
bridge_host2sw_pulse_cnt[j*8+7:j*8] <= bridge_host2sw_pulse_cnt[j*8+7:j*8] + 1'b1;
end
end
end
endgenerate
reg [5*8+7:0] bridge_sw2host_pulse_cnt='b0;
generate
genvar k;
for(k=0;k<=5;k=k+1)begin
always @ (posedge sys_clk)begin
if(cnt_clr)begin
bridge_sw2host_pulse_cnt[k*8+7:k*8] <= 8'b0;
end else if(bridge_sw2host_pulse[k])begin
bridge_sw2host_pulse_cnt[k*8+7:k*8] <= bridge_sw2host_pulse_cnt[k*8+7:k*8] + 1'b1;
end
end
end
endgenerate
wire [5:0] eth_user_pls;
assign eth_user_pls = {sw_eth_user_pls,host_eth_user_pls};
reg [5*8+7:0] eth_user_pls_cnt='b0;
generate
genvar m;
for(m=0;m<=5;m=m+1)begin
always @ (posedge sys_clk)begin
if(cnt_clr)begin
eth_user_pls_cnt[m*8+7:m*8] <= 8'b0;
end else if(eth_user_pls[m])begin
eth_user_pls_cnt[m*8+7:m*8] <= eth_user_pls_cnt[m*8+7:m*8] + 1'b1;
end
end
end
endgenerate
//debug cnt==========
// I/O Connections assignments
assign S_AXI_AWREADY = axi_awready;
assign S_AXI_WREADY = axi_wready;
assign S_AXI_BRESP = 2'b0;//axi_bresp;
assign S_AXI_BVALID = axi_bvalid;
assign S_AXI_ARREADY = axi_arready;
assign S_AXI_RDATA = axi_rdata;
assign S_AXI_RRESP = 2'b0;//axi_rresp;
assign S_AXI_RVALID = axi_rvalid;
// Implement axi_awready generation
// axi_awready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
// de-asserted when reset is low.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_awready <= 1'b0;
aw_en <= 1'b1;
end
else
begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
begin
// slave is ready to accept write address when
// there is a valid write address and write data
// on the write address and data bus. This design
// expects no outstanding transactions.
axi_awready <= 1'b1;
aw_en <= 1'b0;
end
else if (S_AXI_BREADY && axi_bvalid)
begin
aw_en <= 1'b1;
axi_awready <= 1'b0;
end
else
begin
axi_awready <= 1'b0;
end
end
end
// Implement axi_addr latching
// This process is used to latch the address when both
// S_AXI_AWVALID and S_AXI_WVALID are valid.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_addr <= 0;
axi_wdata <= 0;
axi_rw <= 0;
end
else
begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
begin
// Write Address latching
axi_addr <= S_AXI_AWADDR;
axi_wdata <= S_AXI_WDATA;
axi_rw <= 1'b0;
end
else if(~axi_arready && S_AXI_ARVALID)begin
axi_addr <= S_AXI_ARADDR;
axi_rw <= 1'b1;
end
end
end
// Implement axi_wready generation
// axi_wready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
// de-asserted when reset is low.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_wready <= 1'b0;
end
else
begin
if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID && aw_en )
begin
// slave is ready to accept write data when
// there is a valid write address and write data
// on the write address and data bus. This design
// expects no outstanding transactions.
axi_wready <= 1'b1;
end
else
begin
axi_wready <= 1'b0;
end
end
end
// Implement memory mapped register select and write logic generation
// The write data is accepted and written to memory mapped registers when
// axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
// select byte enables of slave registers while writing.
// These registers are cleared when reset (active low) is applied.
// Slave register write enable is asserted when valid address and data are available
// and the slave is ready to accept the write address and write data.
always @( posedge S_AXI_ACLK )begin
slv_reg_wren <= axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID && (axi_addr[16]==1'b0) && (axi_addr[15:14]!=2'b11);
slv_reg_wren_magic <= axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID && (axi_addr[16]==1'b0) && (axi_addr[15:14]!=2'b11) && (axi_wdata[31:24]==8'h5a);
end
//2sw
parameter p_line0_en = 16'h0000;
parameter p_line0_data_baseadrs = 16'h0004;
parameter p_line0_mesg_baseadrs = 16'h0008;
parameter p_line0_fpgawr_point_baseadrs = 16'h000c;
parameter p_line0_depth_define = 16'h0010;
parameter p_line0_mesg_toutcfg = 16'h0014;
parameter p_line0_cpu_point = 16'h0018;
parameter p_line0_fpga_point = 16'h001c;
//2host
parameter p_line1_en = 16'h0020;
parameter p_line1_data_baseadrs = 16'h0024;
parameter p_line1_mesg_baseadrs = 16'h0028;
parameter p_line1_fpgawr_point_baseadrs = 16'h002c;
parameter p_line1_depth_define = 16'h0030;
parameter p_line1_mesg_toutcfg = 16'h0034;
parameter p_line1_cpu_point = 16'h0038;
parameter p_line1_fpga_point = 16'h003c;
//2arm
parameter p_line2_en = 16'h0040;
parameter p_line2_data_baseadrs = 16'h0044;
parameter p_line2_mesg_baseadrs = 16'h0048;
parameter p_line2_fpgawr_point_baseadrs = 16'h004c;
parameter p_line2_depth_define = 16'h0050;
parameter p_line2_mesg_toutcfg = 16'h0054;
parameter p_line2_cpu_point = 16'h0058;
parameter p_line2_fpga_point = 16'h005c;
//arm2HighPrior
parameter p_line3_en = 16'h0060;
parameter p_line3_data_baseadrs = 16'h0064;
parameter p_line3_mesg_baseadrs = 16'h0068;
parameter p_line3_fpgawr_point_baseadrs = 16'h006c;
parameter p_line3_depth_define = 16'h0070;
parameter p_line3_mesg_toutcfg = 16'h0074;
parameter p_line3_cpu_point = 16'h0078;
parameter p_line3_fpga_point = 16'h007c;
//arm2LowPrior
parameter p_line4_en = 16'h0080;
parameter p_line4_data_baseadrs = 16'h0084;
parameter p_line4_mesg_baseadrs = 16'h0088;
parameter p_line4_fpgawr_point_baseadrs = 16'h008c;
parameter p_line4_depth_define = 16'h0090;
parameter p_line4_mesg_toutcfg = 16'h0094;
parameter p_line4_cpu_point = 16'h0098;
parameter p_line4_fpga_point = 16'h009c;
//version
parameter p_version = 16'h00a0;
parameter p_time = 16'h00a4;
parameter p_test_reg = 16'h00a8;
//eeprom
`ifdef eeprom_on
parameter p_eeprom_ctrl = 16'h00b0;
parameter p_eeprom_addr = 16'h00b4;
parameter p_eeprom_wdata = 16'h00b8;
parameter p_eeprom_rdata = 16'h00bc;
//GPIO
parameter p_EEPROM_WP = 16'h00c0;
`endif
parameter p_PCB_ID = 16'h00c4;
parameter p_DEBUG_TEST = 16'h00c8;
parameter p_eMMC_RST = 16'h00cc;
parameter p_FAN_OPEN = 16'h00d0;
parameter p_PHY_ETH_STATUS = 16'h00d4;
parameter p_PHY_PORT0_RST = 16'h00d8;
parameter p_PHY_PORT1_RST = 16'h00dc;
parameter p_LED_R_G = 16'h00e0;
parameter p_TEMPERATURE_CHAN = 16'h00e8;
parameter p_TEMPERATURE_ADC = 16'h00ec;
parameter p_arm_mac_L = 16'h00f0;
parameter p_arm_mac_H = 16'h00f4;
parameter p_DFT_mode = 16'h00f8;
parameter p_pls_cnt = 16'h0100;
parameter p_ready_state = 16'h01F8;
parameter p_cnt_clr = 16'h01FC;
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
oline0_en <= 1'b0;
oline0_data_baseadrs <= 20'b0;
oline0_mesg_baseadrs <= 20'b0;
oline0_fpgawr_point_baseadrs <= 20'b0;
oline0_depth_define <= 2'b11; //default:1K,sysclk=200MHz
oline0_mesg_toutcfg <= 8'h80; //default:128*1.2us=0.15ms
oline0_cpu_point <= 10'b0;
oline1_en <= 1'b0;
oline1_data_baseadrs <= 20'b0;
oline1_mesg_baseadrs <= 20'b0;
oline1_fpgawr_point_baseadrs <= 20'b0;
oline1_depth_define <= 2'b11; //default:1K,sysclk=200MHz
oline1_mesg_toutcfg <= 8'h80; //default:128*1.2us=0.15ms
oline1_cpu_point <= 10'b0;
oline2_en <= 1'b0;
oline2_data_baseadrs <= 20'b0;
oline2_mesg_baseadrs <= 20'b0;
oline2_fpgawr_point_baseadrs <= 20'b0;
oline2_depth_define <= 2'b11; //default:1K,sysclk=200MHz
oline2_mesg_toutcfg <= 8'h80; //default:128*1.2us=0.15ms
oline2_cpu_point <= 10'b0;
oline3_en <= 1'b0;
oline3_data_baseadrs <= 20'b0;
oline3_mesg_baseadrs <= 20'b0;
oline3_fpgawr_point_baseadrs <= 20'b0;
oline3_depth_define <= 2'b11; //default:1K,sysclk=200MHz
oline3_mesg_toutcfg <= 8'h80; //default:128*1.2us=0.15ms
oline3_cpu_point <= 10'b0;
oline4_en <= 1'b0;
oline4_data_baseadrs <= 20'b0;
oline4_mesg_baseadrs <= 20'b0;
oline4_fpgawr_point_baseadrs <= 20'b0;
oline4_depth_define <= 2'b11; //default:1K,sysclk=200MHz
oline4_mesg_toutcfg <= 8'h80; //default:128*1.2us=0.15ms
oline4_cpu_point <= 10'b0;
//version
test_reg <= 16'h1234;
//eeprom
`ifdef eeprom_on
i2c_opt_en <= 1'b0;
i2c_opt_wr <= 1'b0;
i2c_addr <= 16'b0;
i2c_wrdata <= 16'b0;
//GPIO
EEPROM_WP <= 1'b0;
`endif
eMMC_RST <= 1'b0;
FAN_OPEN <= 1'b1;
PHY_PORT0_RST <= 1'b1;
PHY_PORT1_RST <= 1'b1;
RUN_LED_G <= 1'b1;
RUN_LED_R <= 1'b1;
USB_LED_G <= 1'b1;
USB_LED_R <= 1'b1;
xadc_daddr_in <= 7'b0;
arm_mac <= 48'HFFFFFFFFFFFF;
DFT_mode <= 2'b0;
eth_host_sys_loop <= 1'b0;
eth_sw_sys_loop <= 1'b0;
eth_host_line_loop <= 1'b0;
eth_sw_line_loop <= 1'b0;
cnt_clr <= 1'b0;
host_selftest_flag <= 1'b0;
sw_selftest_flag <= 1'b0;
end
else begin
if (slv_reg_wren_magic==1'b1)
begin
case ( axi_addr[15:0] )
p_line0_en : oline0_en <= axi_wdata[0];
p_line0_data_baseadrs : oline0_data_baseadrs <= axi_wdata[19:0];
p_line0_mesg_baseadrs : oline0_mesg_baseadrs <= axi_wdata[19:0];
p_line0_fpgawr_point_baseadrs : oline0_fpgawr_point_baseadrs <= axi_wdata[19:0];
//p_line0_depth_define : oline0_depth_define <= axi_wdata[01:0];
//p_line0_mesg_toutcfg : oline0_mesg_toutcfg <= axi_wdata[07:0];
p_line0_cpu_point : oline0_cpu_point <= axi_wdata[09:0];
p_line1_en : oline1_en <= axi_wdata[0];
p_line1_data_baseadrs : oline1_data_baseadrs <= axi_wdata[19:0];
p_line1_mesg_baseadrs : oline1_mesg_baseadrs <= axi_wdata[19:0];
p_line1_fpgawr_point_baseadrs : oline1_fpgawr_point_baseadrs <= axi_wdata[19:0];
//p_line1_depth_define : oline1_depth_define <= axi_wdata[01:0];
//p_line1_mesg_toutcfg : oline1_mesg_toutcfg <= axi_wdata[07:0];
p_line1_cpu_point : oline1_cpu_point <= axi_wdata[09:0];
p_line2_en : oline2_en <= axi_wdata[0];
p_line2_data_baseadrs : oline2_data_baseadrs <= axi_wdata[19:0];
p_line2_mesg_baseadrs : oline2_mesg_baseadrs <= axi_wdata[19:0];
p_line2_fpgawr_point_baseadrs : oline2_fpgawr_point_baseadrs <= axi_wdata[19:0];
p_line2_depth_define : oline2_depth_define <= axi_wdata[01:0];
p_line2_mesg_toutcfg : oline2_mesg_toutcfg <= axi_wdata[07:0];
p_line2_cpu_point : oline2_cpu_point <= axi_wdata[09:0];
p_line3_en : oline3_en <= axi_wdata[0];
p_line3_data_baseadrs : oline3_data_baseadrs <= axi_wdata[19:0];
p_line3_mesg_baseadrs : oline3_mesg_baseadrs <= axi_wdata[19:0];
p_line3_fpgawr_point_baseadrs : oline3_fpgawr_point_baseadrs <= axi_wdata[19:0];
//p_line3_depth_define : oline3_depth_define <= axi_wdata[01:0];
//p_line3_mesg_toutcfg : oline3_mesg_toutcfg <= axi_wdata[07:0];
p_line3_cpu_point : oline3_cpu_point <= axi_wdata[09:0];
p_line4_en : oline4_en <= axi_wdata[0];
p_line4_data_baseadrs : oline4_data_baseadrs <= axi_wdata[19:0];
p_line4_mesg_baseadrs : oline4_mesg_baseadrs <= axi_wdata[19:0];
p_line4_fpgawr_point_baseadrs : oline4_fpgawr_point_baseadrs <= axi_wdata[19:0];
//p_line4_depth_define : oline4_depth_define <= axi_wdata[01:0];
//p_line4_mesg_toutcfg : oline4_mesg_toutcfg <= axi_wdata[07:0];
p_line4_cpu_point : oline4_cpu_point <= axi_wdata[09:0];
//version
p_test_reg : test_reg <= ~axi_wdata[15:0];
//eeprom
`ifdef eeprom_on
p_eeprom_ctrl : begin
i2c_opt_en <= axi_wdata[4];
i2c_opt_wr <= axi_wdata[0];
end
p_eeprom_addr : i2c_addr <= axi_wdata[15:0];
p_eeprom_wdata : i2c_wrdata <= axi_wdata[15:0];
//GPIO
p_EEPROM_WP : EEPROM_WP <= axi_wdata[0];
`endif
p_eMMC_RST : eMMC_RST <= axi_wdata[0];
p_FAN_OPEN : FAN_OPEN <= axi_wdata[0];
p_PHY_PORT0_RST : PHY_PORT0_RST <= axi_wdata[0];
p_PHY_PORT1_RST : PHY_PORT1_RST <= axi_wdata[0];
p_LED_R_G : {RUN_LED_G,RUN_LED_R,USB_LED_G,USB_LED_R} <= axi_wdata[3:0];
p_TEMPERATURE_CHAN : xadc_daddr_in <= axi_wdata[6:0];
p_arm_mac_L : arm_mac[23:00] <= axi_wdata[23:0];
p_arm_mac_H : arm_mac[47:24] <= axi_wdata[23:0];
p_DFT_mode : begin
DFT_mode <= axi_wdata[1:0];
eth_host_sys_loop<= axi_wdata[4];
eth_sw_sys_loop<= axi_wdata[5];
eth_host_line_loop<= axi_wdata[8];
eth_sw_line_loop<= axi_wdata[9];
host_selftest_flag<= axi_wdata[12];
sw_selftest_flag<= axi_wdata[13];
end
p_cnt_clr : cnt_clr <= axi_wdata[0];
default : ;
endcase
end
end
end
// Implement write response logic generation
// The write response and response valid signals are asserted by the slave
// when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
// This marks the acceptance of address and indicates the status of
// write transaction.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_bvalid <= 0;
//axi_bresp <= 2'b0;
end
else
begin
//if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
if(slv_reg_wren && ~axi_bvalid)
begin
// indicates a valid write response is available
axi_bvalid <= 1'b1;
//axi_bresp <= 2'b0; // 'OKAY' response
end // work error responses in future
else if((ilbus_ack_p0|ilbus_ack_p1|ilbus_ack_p2|ilbus_ack_p3) && axi_rw==1'b0)begin
axi_bvalid <= 1'b1;
end
else
begin
if (S_AXI_BREADY && axi_bvalid)
//check if bready is asserted while bvalid is high)
//(there is a possibility that bready is always asserted high)
begin
axi_bvalid <= 1'b0;
end
end
end
end
// Implement axi_arready generation
// axi_arready is asserted for one S_AXI_ACLK clock cycle when
// S_AXI_ARVALID is asserted. axi_awready is
// de-asserted when reset (active low) is asserted.
// The read address is also latched when S_AXI_ARVALID is
// asserted. axi_araddr is reset to zero on reset assertion.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_arready <= 1'b0;
//axi_araddr <= 32'b0;
end
else
begin
if (~axi_arready && S_AXI_ARVALID)
begin
// indicates that the slave has acceped the valid read address
axi_arready <= 1'b1;
// Read address latching
//axi_araddr <= S_AXI_ARADDR;
end
else
begin
axi_arready <= 1'b0;
end
end
end
// Implement axi_arvalid generation
// axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_ARVALID and axi_arready are asserted. The slave registers
// data are available on the axi_rdata bus at this instance. The
// assertion of axi_rvalid marks the validity of read data on the
// bus and axi_rresp indicates the status of read transaction.axi_rvalid
// is deasserted on reset (active low). axi_rresp and axi_rdata are
// cleared to zero on reset (active low).
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_rvalid <= 0;
//axi_rresp <= 0;
end
else
begin
//if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
if(slv_reg_rden)
begin
// Valid read data is available at the read data bus
axi_rvalid <= 1'b1;
//axi_rresp <= 2'b0; // 'OKAY' response
end
else if((ilbus_ack_p0|ilbus_ack_p1|ilbus_ack_p2|ilbus_ack_p3) && axi_rw==1'b1)begin
axi_rvalid <= 1'b1;
end
else if (axi_rvalid && S_AXI_RREADY)
begin
// Read data is accepted by the master
axi_rvalid <= 1'b0;
end
end
end
// Implement memory mapped register select and read logic generation
// Slave register read enable is asserted when valid address is available
// and the slave is ready to accept the read address.
always @( posedge S_AXI_ACLK )begin
slv_reg_rden <= axi_arready & S_AXI_ARVALID & ~axi_rvalid & (axi_addr[16]==1'b0) & (axi_addr[15:14]!=2'b11);
end
always @( posedge S_AXI_ACLK )
begin
// Address decoding for reading registers
case ( axi_addr[15:0] )
p_line0_en : reg_data_out_00xx <= oline0_en ;
p_line0_data_baseadrs : reg_data_out_00xx <= oline0_data_baseadrs ;
p_line0_mesg_baseadrs : reg_data_out_00xx <= oline0_mesg_baseadrs ;
p_line0_fpgawr_point_baseadrs : reg_data_out_00xx <= oline0_fpgawr_point_baseadrs ;
p_line0_depth_define : reg_data_out_00xx <= oline0_depth_define ;
p_line0_mesg_toutcfg : reg_data_out_00xx <= oline0_mesg_toutcfg ;
p_line0_cpu_point : reg_data_out_00xx <= oline0_cpu_point ;
p_line0_fpga_point : reg_data_out_00xx <= iline0_fpga_point ;
p_line1_en : reg_data_out_00xx <= oline1_en ;
p_line1_data_baseadrs : reg_data_out_00xx <= oline1_data_baseadrs ;
p_line1_mesg_baseadrs : reg_data_out_00xx <= oline1_mesg_baseadrs ;
p_line1_fpgawr_point_baseadrs : reg_data_out_00xx <= oline1_fpgawr_point_baseadrs ;
p_line1_depth_define : reg_data_out_00xx <= oline1_depth_define ;
p_line1_mesg_toutcfg : reg_data_out_00xx <= oline1_mesg_toutcfg ;
p_line1_cpu_point : reg_data_out_00xx <= oline1_cpu_point ;
p_line1_fpga_point : reg_data_out_00xx <= iline1_fpga_point ;
p_line2_en : reg_data_out_00xx <= oline2_en ;
p_line2_data_baseadrs : reg_data_out_00xx <= oline2_data_baseadrs ;
p_line2_mesg_baseadrs : reg_data_out_00xx <= oline2_mesg_baseadrs ;
p_line2_fpgawr_point_baseadrs : reg_data_out_00xx <= oline2_fpgawr_point_baseadrs ;
p_line2_depth_define : reg_data_out_00xx <= oline2_depth_define ;
p_line2_mesg_toutcfg : reg_data_out_00xx <= oline2_mesg_toutcfg ;
p_line2_cpu_point : reg_data_out_00xx <= oline2_cpu_point ;
p_line2_fpga_point : reg_data_out_00xx <= iline2_fpga_point ;
p_line3_en : reg_data_out_00xx <= oline3_en ;
p_line3_data_baseadrs : reg_data_out_00xx <= oline3_data_baseadrs ;
p_line3_mesg_baseadrs : reg_data_out_00xx <= oline3_mesg_baseadrs ;
p_line3_fpgawr_point_baseadrs : reg_data_out_00xx <= oline3_fpgawr_point_baseadrs ;
p_line3_depth_define : reg_data_out_00xx <= oline3_depth_define ;
p_line3_mesg_toutcfg : reg_data_out_00xx <= oline3_mesg_toutcfg ;
p_line3_cpu_point : reg_data_out_00xx <= oline3_cpu_point ;
p_line3_fpga_point : reg_data_out_00xx <= iline3_fpga_point ;
p_line4_en : reg_data_out_00xx <= oline4_en ;
p_line4_data_baseadrs : reg_data_out_00xx <= oline4_data_baseadrs ;
p_line4_mesg_baseadrs : reg_data_out_00xx <= oline4_mesg_baseadrs ;
p_line4_fpgawr_point_baseadrs : reg_data_out_00xx <= oline4_fpgawr_point_baseadrs ;
p_line4_depth_define : reg_data_out_00xx <= oline4_depth_define ;
p_line4_mesg_toutcfg : reg_data_out_00xx <= oline4_mesg_toutcfg ;
p_line4_cpu_point : reg_data_out_00xx <= oline4_cpu_point ;
p_line4_fpga_point : reg_data_out_00xx <= iline4_fpga_point ;
//version
p_version : reg_data_out_00xx <= 32'h00020001 ;
p_time : reg_data_out_00xx <= 32'h20200301 ;
p_test_reg : reg_data_out_00xx <= test_reg;
//eeprom
`ifdef eeprom_on
p_eeprom_ctrl : reg_data_out_00xx <= {i2c_rdy_load,3'b0,i2c_opt_en,3'b0,i2c_opt_wr};
p_eeprom_addr : reg_data_out_00xx <= i2c_addr;
p_eeprom_wdata : reg_data_out_00xx <= i2c_wrdata;
p_eeprom_rdata : reg_data_out_00xx <= i2c_rddata;
16'h00ac : reg_data_out_00xx <= fsm_sft;
//GPIO
p_EEPROM_WP : reg_data_out_00xx <= EEPROM_WP;
`endif
p_PCB_ID : reg_data_out_00xx <= {PCB_ID2,PCB_ID1,PCB_ID0};
p_DEBUG_TEST : reg_data_out_00xx <= DEBUG_TEST;
p_eMMC_RST : reg_data_out_00xx <= eMMC_RST;
p_FAN_OPEN : reg_data_out_00xx <= FAN_OPEN;
p_PHY_ETH_STATUS : reg_data_out_00xx <= {8'b0,
7'b0,PHY_DEBUG_INT,
6'h0,PHY_PORT1_LED2,PHY_PORT1_INT,
6'h0,PHY_PORT0_LED2,PHY_PORT0_INT};
p_PHY_PORT0_RST : reg_data_out_00xx <= PHY_PORT0_RST;
p_PHY_PORT1_RST : reg_data_out_00xx <= PHY_PORT1_RST;
p_LED_R_G : reg_data_out_00xx <= {RUN_LED_G,RUN_LED_R,USB_LED_G,USB_LED_R};
p_TEMPERATURE_CHAN : reg_data_out_00xx <= xadc_daddr_in;
p_TEMPERATURE_ADC : reg_data_out_00xx <= do_out_load;
p_arm_mac_L : reg_data_out_00xx <= arm_mac[23:00];
p_arm_mac_H : reg_data_out_00xx <= arm_mac[47:24];
p_DFT_mode : reg_data_out_00xx <= {sw_self_check_err,host_self_check_err,
2'b0,sw_selftest_flag,host_selftest_flag,2'b0,eth_sw_line_loop,eth_host_line_loop,2'b0,eth_sw_sys_loop,eth_host_sys_loop,2'b0,DFT_mode};
default : reg_data_out_00xx <= 32'h81828384;
endcase
end
always @( posedge S_AXI_ACLK )
begin
// Address decoding for reading registers
case ( axi_addr[15:0] )
p_pls_cnt+8'h00 : reg_data_out_01xx <= dma_pulse_cnt[00*8+7:00*8];
p_pls_cnt+8'h04 : reg_data_out_01xx <= dma_pulse_cnt[01*8+7:01*8];
p_pls_cnt+8'h08 : reg_data_out_01xx <= dma_pulse_cnt[02*8+7:02*8];
p_pls_cnt+8'h0C : reg_data_out_01xx <= dma_pulse_cnt[03*8+7:03*8];
p_pls_cnt+8'h10 : reg_data_out_01xx <= dma_pulse_cnt[04*8+7:04*8];
p_pls_cnt+8'h14 : reg_data_out_01xx <= dma_pulse_cnt[05*8+7:05*8];
p_pls_cnt+8'h18 : reg_data_out_01xx <= dma_pulse_cnt[06*8+7:06*8];
p_pls_cnt+8'h1C : reg_data_out_01xx <= dma_pulse_cnt[07*8+7:07*8];
p_pls_cnt+8'h20 : reg_data_out_01xx <= dma_pulse_cnt[08*8+7:08*8];
p_pls_cnt+8'h24 : reg_data_out_01xx <= dma_pulse_cnt[09*8+7:09*8];
p_pls_cnt+8'h28 : reg_data_out_01xx <= dma_pulse_cnt[10*8+7:10*8];
p_pls_cnt+8'h2C : reg_data_out_01xx <= dma_pulse_cnt[11*8+7:11*8];
p_pls_cnt+8'h30 : reg_data_out_01xx <= dma_pulse_cnt[12*8+7:12*8];
p_pls_cnt+8'h34 : reg_data_out_01xx <= dma_pulse_cnt[13*8+7:13*8];
p_pls_cnt+8'h38 : reg_data_out_01xx <= dma_pulse_cnt[14*8+7:14*8];
p_pls_cnt+8'h3C : reg_data_out_01xx <= dma_pulse_cnt[15*8+7:15*8];
p_pls_cnt+8'h40 : reg_data_out_01xx <= dma_pulse_cnt[16*8+7:16*8];
p_pls_cnt+8'h44 : reg_data_out_01xx <= dma_pulse_cnt[17*8+7:17*8];
p_pls_cnt+8'h48 : reg_data_out_01xx <= dma_pulse_cnt[18*8+7:18*8];
p_pls_cnt+8'h4C : reg_data_out_01xx <= dma_pulse_cnt[19*8+7:19*8];
p_pls_cnt+8'h50 : reg_data_out_01xx <= dma_pulse_cnt[20*8+7:20*8];
p_pls_cnt+8'h54 : reg_data_out_01xx <= dma_pulse_cnt[21*8+7:21*8];
p_pls_cnt+8'h58 : reg_data_out_01xx <= dma_state;
p_pls_cnt+8'h60 : reg_data_out_01xx <= {4'b0,table3_cnt_inused[11:0],4'b0,table3_cnt_pushout[11:0]};
p_pls_cnt+8'h64 : reg_data_out_01xx <= {4'b0,table5_cnt_inused[11:0],4'b0,table5_cnt_pushout[11:0]};
p_pls_cnt+8'h80 : reg_data_out_01xx <= bridge_host2sw_pulse_cnt[0*8+7:0*8];
p_pls_cnt+8'h84 : reg_data_out_01xx <= bridge_host2sw_pulse_cnt[1*8+7:1*8];
p_pls_cnt+8'h88 : reg_data_out_01xx <= bridge_host2sw_pulse_cnt[2*8+7:2*8];
p_pls_cnt+8'h8C : reg_data_out_01xx <= bridge_host2sw_pulse_cnt[3*8+7:3*8];
p_pls_cnt+8'h90 : reg_data_out_01xx <= bridge_host2sw_pulse_cnt[4*8+7:4*8];
p_pls_cnt+8'h94 : reg_data_out_01xx <= bridge_host2sw_pulse_cnt[5*8+7:5*8];
p_pls_cnt+8'h98 : reg_data_out_01xx <= bridge_host2sw_pulse_cnt[6*8+7:6*8];
p_pls_cnt+8'h9C : reg_data_out_01xx <= bridge_host2sw_pulse_cnt[7*8+7:7*8];
p_pls_cnt+8'hC0 : reg_data_out_01xx <= bridge_sw2host_pulse_cnt[0*8+7:0*8];
p_pls_cnt+8'hC4 : reg_data_out_01xx <= bridge_sw2host_pulse_cnt[1*8+7:1*8];
p_pls_cnt+8'hC8 : reg_data_out_01xx <= bridge_sw2host_pulse_cnt[2*8+7:2*8];
p_pls_cnt+8'hCC : reg_data_out_01xx <= bridge_sw2host_pulse_cnt[3*8+7:3*8];
p_pls_cnt+8'hD0 : reg_data_out_01xx <= bridge_sw2host_pulse_cnt[4*8+7:4*8];
p_pls_cnt+8'hD4 : reg_data_out_01xx <= bridge_sw2host_pulse_cnt[5*8+7:5*8];
p_pls_cnt+8'hE0 : reg_data_out_01xx <= eth_user_pls_cnt[0*8+7:0*8];
p_pls_cnt+8'hE4 : reg_data_out_01xx <= eth_user_pls_cnt[1*8+7:1*8];
p_pls_cnt+8'hE8 : reg_data_out_01xx <= eth_user_pls_cnt[2*8+7:2*8];
p_pls_cnt+8'hEC : reg_data_out_01xx <= eth_user_pls_cnt[3*8+7:3*8];
p_pls_cnt+8'hF0 : reg_data_out_01xx <= eth_user_pls_cnt[4*8+7:4*8];
p_pls_cnt+8'hF4 : reg_data_out_01xx <= eth_user_pls_cnt[5*8+7:5*8];
p_ready_state : reg_data_out_01xx <= iready_other_state;
p_cnt_clr : reg_data_out_01xx <= cnt_clr;
default : reg_data_out_01xx <= 32'h81828384;
endcase
end
// Output register or memory read data
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_rdata <= 0;
end
else if(ilbus_ack_p0==1'b1)begin
axi_rdata <= ilbus_rdata_p0;
end
else if(ilbus_ack_p1==1'b1)begin
axi_rdata <= ilbus_rdata_p1;
end
else if(ilbus_ack_p2==1'b1)begin
axi_rdata <= ilbus_rdata_p2;
end
else if(ilbus_ack_p3==1'b1)begin
axi_rdata <= ilbus_rdata_p3;
end
else
begin
// When there is a valid read address (S_AXI_ARVALID) with
// acceptance of read address by the slave (axi_arready)
// output the read dada
if (slv_reg_rden)
begin
axi_rdata <= (axi_addr[8])?reg_data_out_01xx:reg_data_out_00xx; // register read data
end
end
end
// Add user logic here
always @( posedge S_AXI_ACLK )begin
if(S_AXI_ARESETN==1'b0)begin
axi_req_p0 <= 1'b0;
end else begin
if(axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID && (axi_addr[16]==1'b0) && (axi_addr[15:12]==4'b1110))begin
axi_req_p0 <= 1'b1;
end else if(axi_arready & S_AXI_ARVALID & ~axi_rvalid & (axi_addr[16]==1'b0) & (axi_addr[15:12]==4'b1110))begin
axi_req_p0 <= 1'b1;
end else if(ilbus_ack_p0)begin
axi_req_p0 <= 1'b0;
end
end
end
always @( posedge S_AXI_ACLK )begin
if(S_AXI_ARESETN==1'b0)begin
axi_req_p1 <= 1'b0;
end else begin
if(axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID && (axi_addr[16]==1'b0) && (axi_addr[15:12]==4'b1111))begin
axi_req_p1 <= 1'b1;
end else if(axi_arready & S_AXI_ARVALID & ~axi_rvalid & (axi_addr[16]==1'b0) & (axi_addr[15:12]==4'b1111))begin
axi_req_p1 <= 1'b1;
end else if(ilbus_ack_p1)begin
axi_req_p1 <= 1'b0;
end
end
end
always @( posedge S_AXI_ACLK )begin
if(S_AXI_ARESETN==1'b0)begin
axi_req_p2 <= 1'b0;
end else begin
if(axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID && (axi_addr[16]==1'b0) && (axi_addr[15:12]==4'hC || axi_addr[15:12]==4'hD))begin
axi_req_p2 <= 1'b1;
end else if(axi_arready & S_AXI_ARVALID & ~axi_rvalid & (axi_addr[16]==1'b0) && (axi_addr[15:12]==4'hC || axi_addr[15:12]==4'hD))begin
axi_req_p2 <= 1'b1;
end else if(ilbus_ack_p2)begin
axi_req_p2 <= 1'b0;
end
end
end
always @( posedge S_AXI_ACLK )begin
if(S_AXI_ARESETN==1'b0)begin
axi_req_p3 <= 1'b0;
end else begin
if(axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID && (axi_addr[16]==1'b1))begin
axi_req_p3 <= 1'b1;
end else if(axi_arready & S_AXI_ARVALID & ~axi_rvalid & (axi_addr[16]==1'b1))begin
axi_req_p3 <= 1'b1;
end else if(ilbus_ack_p3)begin
axi_req_p3 <= 1'b0;
end
end
end
assign olbus_req_p0 = axi_req_p0;
assign olbus_req_p1 = axi_req_p1;
assign olbus_req_p2 = axi_req_p2;
assign olbus_req_p3 = axi_req_p3;
assign olbus_rw = axi_rw;
assign olbus_addr = axi_addr[15:0];
assign olbus_wdata = axi_wdata[31:0];
//eeprom
`ifdef eeprom_on
always @( posedge S_AXI_ACLK )begin
i2c_opt_en_r1 <= i2c_opt_en;
i2c_opt_en_r2 <= i2c_opt_en_r1;
i2c_wr <= i2c_opt_en_r1 & (~i2c_opt_en_r2) & i2c_opt_wr;
i2c_rd <= i2c_opt_en_r1 & (~i2c_opt_en_r2) & (~i2c_opt_wr);
if(S_AXI_ARESETN==1'b0)begin
i2c_rdy_load <= 1'b1;
end else if(i2c_opt_en_r1 & (~i2c_opt_en_r2))begin
i2c_rdy_load <= 1'b0;
end else if(i2c_rdy==1'b1)begin
i2c_rdy_load <= 1'b1;
end
end
eeprom_ctrl eeprom_ctrl (
/*//system */
/*input */ .clk (S_AXI_ACLK),
/*input */ .rst (~S_AXI_ARESETN),
.fsm_sft (fsm_sft),
/*input [7:0] */ .i2c_id (8'ha0),
/*input */ .i2c_wr (i2c_wr),
/*input */ .i2c_rd (i2c_rd),
/*input [15:0] */ .i2c_addr (i2c_addr),
/*input [15:0] */ .i2c_wrdata (i2c_wrdata),
/*output [15:0] */ .i2c_rddata (i2c_rddata),
/*output reg */ .i2c_rdy (i2c_rdy),
/*output */ .i2c_scl (EEPROM_CLK),
/*inout */ .i2c_sda (EEPORM_SDA)
);
`endif
//temperature-xadc
always @( posedge S_AXI_ACLK )begin
if(S_AXI_ARESETN==1'b0)begin
den_cnt <= 4'b0;
den_pls <= 1'b0;
end else begin
den_cnt <= den_cnt + 1'b1;
den_pls <= (den_cnt==4'hF);
end
if(drdy_out)begin
do_out_load <= {1'b1,do_out[15:0]};
end
end
xadc_wiz_0 xadc_wiz_0(
.daddr_in (xadc_daddr_in), // Address bus for the dynamic reconfiguration port
.dclk_in (S_AXI_ACLK), // Clock input for the dynamic reconfiguration port
.den_in (den_pls), // Enable Signal for the dynamic reconfiguration port
.di_in (16'b0), // Input data bus for the dynamic reconfiguration port
.dwe_in (1'b0), // Write Enable for the dynamic reconfiguration port
.reset_in (~S_AXI_ARESETN), // Reset signal for the System Monitor control logic
.busy_out (), // ADC Busy signal
.channel_out (), // Channel Selection Outputs
.do_out (do_out), // Output data bus for dynamic reconfiguration port
.drdy_out (drdy_out), // Data ready signal for the dynamic reconfiguration port
.eoc_out (), // End of Conversion Signal
.eos_out (), // End of Sequence Signal
.ot_out (), // Over-Temperature alarm output
.vccddro_alarm_out (), // VCCDDRO-sensor alarm output
.vccpaux_alarm_out (), // VCCPAUX-sensor alarm output
.vccpint_alarm_out (), // VCCPINT-sensor alarm output
.vccaux_alarm_out (), // VCCAUX-sensor alarm output
.vccint_alarm_out (), // VCCINT-sensor alarm output
.user_temp_alarm_out(), // Temperature-sensor alarm output
.alarm_out (), // OR'ed output of all the Alarms
.vp_in (1'b0), // Dedicated Analog Input Pair
.vn_in (1'b0)
);
// User logic end
endmodule
`timescale 1 ns / 1 ps
module myip_v3 #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Master Bus Interface M00_AXI
parameter C_M00_AXI_TARGET_SLAVE_BASE_ADDR = 32'h40000000,
parameter integer C_M00_AXI_BURST_LEN = 256,
parameter integer C_M00_AXI_ID_WIDTH = 1,
parameter integer C_M00_AXI_ADDR_WIDTH = 32,
parameter integer C_M00_AXI_DATA_WIDTH = 64,
parameter integer C_M00_AXI_AWUSER_WIDTH = 8,
parameter integer C_M00_AXI_ARUSER_WIDTH = 8,
parameter integer C_M00_AXI_WUSER_WIDTH = 8,
parameter integer C_M00_AXI_RUSER_WIDTH = 8,
parameter integer C_M00_AXI_BUSER_WIDTH = 8,
// Parameters of Axi Slave Bus Interface S01_AXI
parameter integer C_S01_AXI_DATA_WIDTH = 32,
parameter integer C_S01_AXI_ADDR_WIDTH = 32
)
(
// Users to add ports here
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Master Bus Interface M00_AXI
input wire m00_axi_aclk,
input wire m00_axi_aresetn,
output wire [C_M00_AXI_ID_WIDTH-1 : 0] m00_axi_awid,
output wire [C_M00_AXI_ADDR_WIDTH-1 : 0] m00_axi_awaddr,
output wire [7 : 0] m00_axi_awlen,
output wire [2 : 0] m00_axi_awsize,
output wire [1 : 0] m00_axi_awburst,
output wire m00_axi_awlock,
output wire [3 : 0] m00_axi_awcache,
output wire [2 : 0] m00_axi_awprot,
output wire [3 : 0] m00_axi_awqos,
output wire [C_M00_AXI_AWUSER_WIDTH-1 : 0] m00_axi_awuser,
output wire m00_axi_awvalid,
input wire m00_axi_awready,
output wire [C_M00_AXI_DATA_WIDTH-1 : 0] m00_axi_wdata,
output wire [C_M00_AXI_DATA_WIDTH/8-1 : 0] m00_axi_wstrb,
output wire m00_axi_wlast,
output wire [C_M00_AXI_WUSER_WIDTH-1 : 0] m00_axi_wuser,
output wire m00_axi_wvalid,
input wire m00_axi_wready,
input wire [C_M00_AXI_ID_WIDTH-1 : 0] m00_axi_bid,
input wire [1 : 0] m00_axi_bresp,
input wire [C_M00_AXI_BUSER_WIDTH-1 : 0] m00_axi_buser,
input wire m00_axi_bvalid,
output wire m00_axi_bready,
output wire [C_M00_AXI_ID_WIDTH-1 : 0] m00_axi_arid,
output wire [C_M00_AXI_ADDR_WIDTH-1 : 0] m00_axi_araddr,
output wire [7 : 0] m00_axi_arlen,
output wire [2 : 0] m00_axi_arsize,
output wire [1 : 0] m00_axi_arburst,
output wire m00_axi_arlock,
output wire [3 : 0] m00_axi_arcache,
output wire [2 : 0] m00_axi_arprot,
output wire [3 : 0] m00_axi_arqos,
output wire [C_M00_AXI_ARUSER_WIDTH-1 : 0] m00_axi_aruser,
output wire m00_axi_arvalid,
input wire m00_axi_arready,
input wire [C_M00_AXI_ID_WIDTH-1 : 0] m00_axi_rid,
input wire [C_M00_AXI_DATA_WIDTH-1 : 0] m00_axi_rdata,
input wire [1 : 0] m00_axi_rresp,
input wire m00_axi_rlast,
input wire [C_M00_AXI_RUSER_WIDTH-1 : 0] m00_axi_ruser,
input wire m00_axi_rvalid,
output wire m00_axi_rready,
// Ports of Axi Slave Bus Interface S01_AXI
input wire s01_axi_aclk,
input wire s01_axi_aresetn,
input wire [C_S01_AXI_ADDR_WIDTH-1 : 0] s01_axi_awaddr,
input wire [2 : 0] s01_axi_awprot,
input wire s01_axi_awvalid,
output wire s01_axi_awready,
input wire [C_S01_AXI_DATA_WIDTH-1 : 0] s01_axi_wdata,
input wire [(C_S01_AXI_DATA_WIDTH/8)-1 : 0] s01_axi_wstrb,
input wire s01_axi_wvalid,
output wire s01_axi_wready,
output wire [1 : 0] s01_axi_bresp,
output wire s01_axi_bvalid,
input wire s01_axi_bready,
input wire [C_S01_AXI_ADDR_WIDTH-1 : 0] s01_axi_araddr,
input wire [2 : 0] s01_axi_arprot,
input wire s01_axi_arvalid,
output wire s01_axi_arready,
output wire [C_S01_AXI_DATA_WIDTH-1 : 0] s01_axi_rdata,
output wire [1 : 0] s01_axi_rresp,
output wire s01_axi_rvalid,
input wire s01_axi_rready,
output [3:0] host_rgmii_txd,
output host_rgmii_tx_ctl,
output host_rgmii_txc,
input [3:0] host_rgmii_rxd,
input host_rgmii_rx_ctl,
input host_rgmii_rxc,
inout host_mdio,
output host_mdc,
output [3:0] sw_rgmii_txd,
output sw_rgmii_tx_ctl,
output sw_rgmii_txc,
input [3:0] sw_rgmii_rxd,
input sw_rgmii_rx_ctl,
input sw_rgmii_rxc,
inout sw_mdio,
output sw_mdc,
//GPIO-bank34
input PCB_ID0,
input PCB_ID1,
input PCB_ID2,
//GPIO-bank35
input DEBUG_TEST ,
inout EEPORM_SDA ,
output EEPROM_CLK ,
output EEPROM_WP ,
output eMMC_RST ,
output FAN_OPEN ,
input FPGA_PS_50M ,
input PHY_DEBUG_INT ,
input PHY_PORT0_INT ,
input PHY_PORT0_LED2 ,
output PHY_PORT0_RST ,
input PHY_PORT1_INT ,
input PHY_PORT1_LED2 ,
output PHY_PORT1_RST ,
output PORT0_LED_ACT ,
output PORT0_LED_LINK ,
output PORT1_LED_ACT ,
output PORT1_LED_LINK ,
output RUN_LED_G ,
output RUN_LED_R ,
output USB_LED_G ,
output USB_LED_R
);
//hostreg
wire jline0_en;
wire [19:0] jline0_data_baseadrs;
wire [19:0] jline0_mesg_baseadrs;
wire [19:0] jline0_fpgawr_point_baseadrs;
wire [01:0] jline0_depth_define;
wire [07:0] jline0_mesg_toutcfg;
wire [09:0] jline0_cpu_point;
wire [09:0] jline0_fpga_point;
wire jline1_en;
wire [19:0] jline1_data_baseadrs;
wire [19:0] jline1_mesg_baseadrs;
wire [19:0] jline1_fpgawr_point_baseadrs;
wire [01:0] jline1_depth_define;
wire [07:0] jline1_mesg_toutcfg;
wire [09:0] jline1_cpu_point;
wire [09:0] jline1_fpga_point;
wire jline2_en;
wire [19:0] jline2_data_baseadrs;
wire [19:0] jline2_mesg_baseadrs;
wire [19:0] jline2_fpgawr_point_baseadrs;
wire [01:0] jline2_depth_define;
wire [07:0] jline2_mesg_toutcfg;
wire [09:0] jline2_cpu_point;
wire [09:0] jline2_fpga_point;
wire jline3_en;
wire [19:0] jline3_data_baseadrs;
wire [19:0] jline3_mesg_baseadrs;
wire [19:0] jline3_fpgawr_point_baseadrs;
wire [01:0] jline3_depth_define;
wire [07:0] jline3_mesg_toutcfg;
wire [09:0] jline3_cpu_point;
wire [09:0] jline3_fpga_point;
wire jline4_en;
wire [19:0] jline4_data_baseadrs;
wire [19:0] jline4_mesg_baseadrs;
wire [19:0] jline4_fpgawr_point_baseadrs;
wire [01:0] jline4_depth_define;
wire [07:0] jline4_mesg_toutcfg;
wire [09:0] jline4_cpu_point;
wire [09:0] jline4_fpga_point;
wire [31:0] jdma_pulse;
wire [31:0] jdma_state;
wire [7:0] jbridge_host2sw_pulse;
wire [5:0] jbridge_sw2host_pulse;
wire [31:0] jready_other_state;
wire [47:0] arm_mac;
wire [1:0] DFT_mode;
wire eth_host_sys_loop;
wire eth_sw_sys_loop;
wire eth_host_line_loop;
wire eth_sw_line_loop;
wire host_selftest_flag;
wire [7:0] host_self_check_err;
wire sw_selftest_flag;
wire [7:0] sw_self_check_err;
//mac-0/1
wire jlbus_req_p0;
wire jlbus_req_p1;
wire jlbus_req_p2;
wire jlbus_req_p3;
wire jlbus_rw;
wire [15:0] jlbus_addr;
wire [31:0] jlbus_wdata;
wire jlbus_ack_p0;
wire jlbus_ack_p1;
wire jlbus_ack_p2;
wire jlbus_ack_p3;
wire [31:0] jlbus_rdata_p0;
wire [31:0] jlbus_rdata_p1;
wire [31:0] jlbus_rdata_p2;
wire [31:0] jlbus_rdata_p3;
wire [11:0] table3_cnt_inused;
wire [11:0] table3_cnt_pushout;
wire [11:0] table5_cnt_inused;
wire [11:0] table5_cnt_pushout;
//data_if
wire [71:0] dma_data;
wire dma_den;
wire dma_ready;
wire [71:0] cpld_data;
wire cpld_en;
//transform_8b_64b
wire [71:0] recomb_data_2sw;
wire [71:0] recomb_data_2host;
wire [71:0] recomb_data_2arm;
wire recomb_den_2sw;
wire recomb_den_2host;
wire recomb_den_2arm;
//send to ge port
wire [71:0] down_data;
wire down_den_H;
wire down_den_L;
wire down_buf_ready_H;
wire down_buf_ready_L;
//======up stream
//monitor data
wire [08:0] host2sw_datain;
wire [08:0] sw2host_datain;
wire [08:0] sw2arm_datain;
wire host2sw_wen;
wire sw2host_wen;
wire sw2arm_wen;
wire host2sw_werr;
wire sw2host_tx_ready;
wire user_m_rx_ready;
//====down stream
//down
wire [8:0] user_h_rx_datain;
wire user_h_rx_wen;
wire user_h_rx_ready;
wire [8:0] user_l_rx_datain;
wire user_l_rx_wen;
wire user_l_rx_ready;
//bridge
wire [7:0] sw_user_rx_datain;
wire sw_user_rx_eop;
wire sw_user_rx_err;
wire sw_user_rx_wen;
wire sw_user_rx_ready;
wire [8:0] sw_user_tx_datain;
wire sw_user_tx_wen;
wire sw_user_tx_ready;
wire dcm_locked;
wire output_flag_u0;
wire output_flag_u1;
wire output_flag_u2;
wire output_flag_u3;
//eth_op debug
wire [2:0] host_eth_user_pls;
wire [2:0] sw_eth_user_pls;
wire sys_clk;
wire sys_rst;
assign sys_clk = m00_axi_aclk;
assign sys_rst = ~m00_axi_aresetn;
wire cbus_clk;
wire cbus_rst;
assign cbus_clk = s01_axi_aclk;
assign cbus_rst = ~s01_axi_aresetn;
// Instantiation of Axi Bus Interface M00_AXI
myip_v3_M00_AXI # (
.C_M_TARGET_SLAVE_BASE_ADDR(C_M00_AXI_TARGET_SLAVE_BASE_ADDR),
.C_M_AXI_BURST_LEN(C_M00_AXI_BURST_LEN),
.C_M_AXI_ID_WIDTH(C_M00_AXI_ID_WIDTH),
.C_M_AXI_ADDR_WIDTH(C_M00_AXI_ADDR_WIDTH),
.C_M_AXI_DATA_WIDTH(C_M00_AXI_DATA_WIDTH),
.C_M_AXI_AWUSER_WIDTH(C_M00_AXI_AWUSER_WIDTH),
.C_M_AXI_ARUSER_WIDTH(C_M00_AXI_ARUSER_WIDTH),
.C_M_AXI_WUSER_WIDTH(C_M00_AXI_WUSER_WIDTH),
.C_M_AXI_RUSER_WIDTH(C_M00_AXI_RUSER_WIDTH),
.C_M_AXI_BUSER_WIDTH(C_M00_AXI_BUSER_WIDTH)
) myip_v3_M00_AXI_inst (
.M_AXI_ACLK(m00_axi_aclk),
.M_AXI_ARESETN(m00_axi_aresetn),
.M_AXI_AWID(m00_axi_awid),
.M_AXI_AWADDR(m00_axi_awaddr),
.M_AXI_AWLEN(m00_axi_awlen),
.M_AXI_AWSIZE(m00_axi_awsize),
.M_AXI_AWBURST(m00_axi_awburst),
.M_AXI_AWLOCK(m00_axi_awlock),
.M_AXI_AWCACHE(m00_axi_awcache),
.M_AXI_AWPROT(m00_axi_awprot),
.M_AXI_AWQOS(m00_axi_awqos),
.M_AXI_AWUSER(m00_axi_awuser),
.M_AXI_AWVALID(m00_axi_awvalid),
.M_AXI_AWREADY(m00_axi_awready),
.M_AXI_WDATA(m00_axi_wdata),
.M_AXI_WSTRB(m00_axi_wstrb),
.M_AXI_WLAST(m00_axi_wlast),
.M_AXI_WUSER(m00_axi_wuser),
.M_AXI_WVALID(m00_axi_wvalid),
.M_AXI_WREADY(m00_axi_wready),
.M_AXI_BID(m00_axi_bid),
.M_AXI_BRESP(m00_axi_bresp),
.M_AXI_BUSER(m00_axi_buser),
.M_AXI_BVALID(m00_axi_bvalid),
.M_AXI_BREADY(m00_axi_bready),
.M_AXI_ARID(m00_axi_arid),
.M_AXI_ARADDR(m00_axi_araddr),
.M_AXI_ARLEN(m00_axi_arlen),
.M_AXI_ARSIZE(m00_axi_arsize),
.M_AXI_ARBURST(m00_axi_arburst),
.M_AXI_ARLOCK(m00_axi_arlock),
.M_AXI_ARCACHE(m00_axi_arcache),
.M_AXI_ARPROT(m00_axi_arprot),
.M_AXI_ARQOS(m00_axi_arqos),
.M_AXI_ARUSER(m00_axi_aruser),
.M_AXI_ARVALID(m00_axi_arvalid),
.M_AXI_ARREADY(m00_axi_arready),
.M_AXI_RID(m00_axi_rid),
.M_AXI_RDATA(m00_axi_rdata),
.M_AXI_RRESP(m00_axi_rresp),
.M_AXI_RLAST(m00_axi_rlast),
.M_AXI_RUSER(m00_axi_ruser),
.M_AXI_RVALID(m00_axi_rvalid),
.M_AXI_RREADY(m00_axi_rready),
//data_if
/*input [71:0] */ .dma_data (dma_data ),
/*input */ .dma_den (dma_den ),
/*output */ .dma_ready (dma_ready),
/* */
/*output [71:0] */ .cpld_data (cpld_data),
/*output */ .cpld_en (cpld_en )
);
// Instantiation of Axi Bus Interface S01_AXI
myip_v3_S01_AXI # (
.C_S_AXI_DATA_WIDTH(C_S01_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH(C_S01_AXI_ADDR_WIDTH)
) myip_v3_S01_AXI_inst (
.S_AXI_ACLK(s01_axi_aclk),
.S_AXI_ARESETN(s01_axi_aresetn),
.S_AXI_AWADDR(s01_axi_awaddr),
.S_AXI_AWPROT(s01_axi_awprot),
.S_AXI_AWVALID(s01_axi_awvalid),
.S_AXI_AWREADY(s01_axi_awready),
.S_AXI_WDATA(s01_axi_wdata),
.S_AXI_WSTRB(s01_axi_wstrb),
.S_AXI_WVALID(s01_axi_wvalid),
.S_AXI_WREADY(s01_axi_wready),
.S_AXI_BRESP(s01_axi_bresp),
.S_AXI_BVALID(s01_axi_bvalid),
.S_AXI_BREADY(s01_axi_bready),
.S_AXI_ARADDR(s01_axi_araddr),
.S_AXI_ARPROT(s01_axi_arprot),
.S_AXI_ARVALID(s01_axi_arvalid),
.S_AXI_ARREADY(s01_axi_arready),
.S_AXI_RDATA(s01_axi_rdata),
.S_AXI_RRESP(s01_axi_rresp),
.S_AXI_RVALID(s01_axi_rvalid),
.S_AXI_RREADY(s01_axi_rready),
//hostreg
/*output reg */ .oline0_en (jline0_en ),
/*output reg [20:0] */ .oline0_data_baseadrs (jline0_data_baseadrs ),
/*output reg [20:0] */ .oline0_mesg_baseadrs (jline0_mesg_baseadrs ),
/*output reg [20:0] */ .oline0_fpgawr_point_baseadrs (jline0_fpgawr_point_baseadrs),
/*output reg [01:0] */ .oline0_depth_define (jline0_depth_define ),
/*output reg [07:0] */ .oline0_mesg_toutcfg (jline0_mesg_toutcfg ),
/*output reg [09:0] */ .oline0_cpu_point (jline0_cpu_point ),
/*input [09:0] */ .iline0_fpga_point (jline0_fpga_point ),
/* */
/*output reg */ .oline1_en (jline1_en ),
/*output reg [20:0] */ .oline1_data_baseadrs (jline1_data_baseadrs ),
/*output reg [20:0] */ .oline1_mesg_baseadrs (jline1_mesg_baseadrs ),
/*output reg [20:0] */ .oline1_fpgawr_point_baseadrs (jline1_fpgawr_point_baseadrs),
/*output reg [01:0] */ .oline1_depth_define (jline1_depth_define ),
/*output reg [07:0] */ .oline1_mesg_toutcfg (jline1_mesg_toutcfg ),
/*output reg [09:0] */ .oline1_cpu_point (jline1_cpu_point ),
/*input [09:0] */ .iline1_fpga_point (jline1_fpga_point ),
/* */
/*output reg */ .oline2_en (jline2_en ),
/*output reg [20:0] */ .oline2_data_baseadrs (jline2_data_baseadrs ),
/*output reg [20:0] */ .oline2_mesg_baseadrs (jline2_mesg_baseadrs ),
/*output reg [20:0] */ .oline2_fpgawr_point_baseadrs (jline2_fpgawr_point_baseadrs),
/*output reg [01:0] */ .oline2_depth_define (jline2_depth_define ),
/*output reg [07:0] */ .oline2_mesg_toutcfg (jline2_mesg_toutcfg ),
/*output reg [09:0] */ .oline2_cpu_point (jline2_cpu_point ),
/*input [09:0] */ .iline2_fpga_point (jline2_fpga_point ),
/* */
/*output reg */ .oline3_en (jline3_en ),
/*output reg [20:0] */ .oline3_data_baseadrs (jline3_data_baseadrs ),
/*output reg [20:0] */ .oline3_mesg_baseadrs (jline3_mesg_baseadrs ),
/*output reg [20:0] */ .oline3_fpgawr_point_baseadrs (jline3_fpgawr_point_baseadrs),
/*output reg [01:0] */ .oline3_depth_define (jline3_depth_define ),
/*output reg [07:0] */ .oline3_mesg_toutcfg (jline3_mesg_toutcfg ),
/*output reg [09:0] */ .oline3_cpu_point (jline3_cpu_point ),
/*input [09:0] */ .iline3_fpga_point (jline3_fpga_point ),
/* */
/*output reg */ .oline4_en (jline4_en ),
/*output reg [20:0] */ .oline4_data_baseadrs (jline4_data_baseadrs ),
/*output reg [20:0] */ .oline4_mesg_baseadrs (jline4_mesg_baseadrs ),
/*output reg [20:0] */ .oline4_fpgawr_point_baseadrs (jline4_fpgawr_point_baseadrs),
/*output reg [01:0] */ .oline4_depth_define (jline4_depth_define ),
/*output reg [07:0] */ .oline4_mesg_toutcfg (jline4_mesg_toutcfg ),
/*output reg [09:0] */ .oline4_cpu_point (jline4_cpu_point ),
/*input [09:0] */ .iline4_fpga_point (jline4_fpga_point ),
/* */
/*//mac-0/1 */
/*output */ .olbus_req_p0 (jlbus_req_p0 ),
/*output */ .olbus_req_p1 (jlbus_req_p1 ),
/*output */ .olbus_req_p2 (jlbus_req_p2 ),
/*output */ .olbus_req_p3 (jlbus_req_p3 ),
/*output */ .olbus_rw (jlbus_rw ),
/*output [15:0] */ .olbus_addr (jlbus_addr ),
/*output [31:0] */ .olbus_wdata (jlbus_wdata ),
/*input */ .ilbus_ack_p0 (jlbus_ack_p0 ),
/*input */ .ilbus_ack_p1 (jlbus_ack_p1 ),
/*input */ .ilbus_ack_p2 (jlbus_ack_p2 ),
/*input */ .ilbus_ack_p3 (jlbus_ack_p3 ),
/*input [31:0] */ .ilbus_rdata_p0 (jlbus_rdata_p0 ),
/*input [31:0] */ .ilbus_rdata_p1 (jlbus_rdata_p1 ),
/*input [31:0] */ .ilbus_rdata_p2 (jlbus_rdata_p2 ),
/*input [31:0] */ .ilbus_rdata_p3 (jlbus_rdata_p3 ),
/*//GPIO-bank34 */
/*input */ .PCB_ID0 (PCB_ID0),
/*input */ .PCB_ID1 (PCB_ID1),
/*input */ .PCB_ID2 (PCB_ID2),
/*//GPIO-bank35 */
/*input */ .DEBUG_TEST (DEBUG_TEST),
/*inout */ .EEPORM_SDA (EEPORM_SDA),
/*output */ .EEPROM_CLK (EEPROM_CLK),
/*output */ .EEPROM_WP (EEPROM_WP ),
/*output reg */ .eMMC_RST (eMMC_RST ),
/*output reg */ .FAN_OPEN (FAN_OPEN ),
/*input */ .PHY_DEBUG_INT (PHY_DEBUG_INT ),
/*input */ .PHY_PORT0_INT (PHY_PORT0_INT ),
/*input */ .PHY_PORT0_LED2 (PHY_PORT0_LED2),
/*output reg */ .PHY_PORT0_RST (PHY_PORT0_RST ),
/*input */ .PHY_PORT1_INT (PHY_PORT1_INT ),
/*input */ .PHY_PORT1_LED2 (PHY_PORT1_LED2),
/*output reg */ .PHY_PORT1_RST (PHY_PORT1_RST ),
/*output reg */ .RUN_LED_G (RUN_LED_G ),
/*output reg */ .RUN_LED_R (RUN_LED_R ),
/*output reg */ .USB_LED_G (USB_LED_G ),
/*output reg */ .USB_LED_R (USB_LED_R ),
/* */
/*input */ .sys_clk (sys_clk),
/*input [31:0] */ .dma_pulse (jdma_pulse),
/*input [31:0] */ .dma_state (jdma_state),
/*input [7:0] */ .bridge_host2sw_pulse (jbridge_host2sw_pulse),
/*input [5:0] */ .bridge_sw2host_pulse (jbridge_sw2host_pulse),
/*input [31:0] */ .iready_other_state (jready_other_state),
/*input [2:0] */ .host_eth_user_pls (host_eth_user_pls),
/*input [2:0] */ .sw_eth_user_pls (sw_eth_user_pls),
/*output reg [47:0] */ .arm_mac (arm_mac),
/*output reg [1:0] */ .DFT_mode (DFT_mode),
/*output reg */ .eth_host_sys_loop (eth_host_sys_loop),
/*output reg */ .eth_sw_sys_loop (eth_sw_sys_loop),
/*output reg */ .eth_host_line_loop (eth_host_line_loop),
/*output reg */ .eth_sw_line_loop (eth_sw_line_loop),
/*output */ .host_selftest_flag (host_selftest_flag),
/*input [7:0] */ .host_self_check_err (host_self_check_err),
/*output */ .sw_selftest_flag (sw_selftest_flag),
/*input [7:0] */ .sw_self_check_err (sw_self_check_err),
/*input [11:0] */ .table3_cnt_inused (table3_cnt_inused ),
/*input [11:0] */ .table3_cnt_pushout (table3_cnt_pushout),
/*input [11:0] */ .table5_cnt_inused (table5_cnt_inused ),
/*input [11:0] */ .table5_cnt_pushout (table5_cnt_pushout)
);
assign jready_other_state = {output_flag_u3,output_flag_u2,output_flag_u1,output_flag_u0,
1'b0,sw_user_tx_ready,sw2host_tx_ready,dcm_locked,
1'b0,user_l_rx_ready,user_m_rx_ready,user_h_rx_ready,
sw_user_rx_ready,dma_ready,down_buf_ready_L,down_buf_ready_H};
// Add user logic here
dma_ctrl dma_ctrl (
//system
/*input */ .iclk (sys_clk),
/*input */ .irst (sys_rst),
/* */
/*//axi_master */
/*output [71:0] */ .dma_data (dma_data ),
/*output */ .dma_den (dma_den ),
/*input */ .dma_ready (dma_ready ),
/* */
/*input [71:0] */ .cpld_data (cpld_data ),
/*input */ .cpld_en (cpld_en ),
/* */
//transform_8b_64b
/*input [71:0] */ .recomb_data_2sw (recomb_data_2sw ),
/*input [71:0] */ .recomb_data_2host (recomb_data_2host ),
/*input [71:0] */ .recomb_data_2arm (recomb_data_2arm ),
/*input */ .recomb_den_2sw (recomb_den_2sw ),
/*input */ .recomb_den_2host (recomb_den_2host ),
/*input */ .recomb_den_2arm (recomb_den_2arm ),
//send to ge port
/*output [71:0] */ .down_data (down_data ),
/*output */ .down_den_H (down_den_H ),
/*output */ .down_den_L (down_den_L ),
/*input */ .down_buf_ready_H (down_buf_ready_H ),
/*input */ .down_buf_ready_L (down_buf_ready_L ),
/* */
/*//host_reg */
/*input */ .iline0_en (1'b0),//(jline0_en ),
/*input [20:0] */ .iline0_data_baseadrs (jline0_data_baseadrs ),
/*input [20:0] */ .iline0_mesg_baseadrs (jline0_mesg_baseadrs ),
/*input [20:0] */ .iline0_fpgawr_point_baseadrs (jline0_fpgawr_point_baseadrs),
/*input [1:0] */ .iline0_depth_define (jline0_depth_define ),
/*input [7:0] */ .iline0_mesg_toutcfg (jline0_mesg_toutcfg ),
/*input [9:0] */ .iline0_cpu_point (jline0_cpu_point ),
/*output [9:0] */ .oline0_fpga_point (jline0_fpga_point ),
/* */
/*input */ .iline1_en (1'b0),//(jline1_en ),
/*input [20:0] */ .iline1_data_baseadrs (jline1_data_baseadrs ),
/*input [20:0] */ .iline1_mesg_baseadrs (jline1_mesg_baseadrs ),
/*input [20:0] */ .iline1_fpgawr_point_baseadrs (jline1_fpgawr_point_baseadrs),
/*input [1:0] */ .iline1_depth_define (jline1_depth_define ),
/*input [7:0] */ .iline1_mesg_toutcfg (jline1_mesg_toutcfg ),
/*input [9:0] */ .iline1_cpu_point (jline1_cpu_point ),
/*output [9:0] */ .oline1_fpga_point (jline1_fpga_point ),
/* */
/*input */ .iline2_en (jline2_en ),
/*input [20:0] */ .iline2_data_baseadrs (jline2_data_baseadrs ),
/*input [20:0] */ .iline2_mesg_baseadrs (jline2_mesg_baseadrs ),
/*input [20:0] */ .iline2_fpgawr_point_baseadrs (jline2_fpgawr_point_baseadrs),
/*input [1:0] */ .iline2_depth_define (jline2_depth_define ),
/*input [7:0] */ .iline2_mesg_toutcfg (jline2_mesg_toutcfg ),
/*input [9:0] */ .iline2_cpu_point (jline2_cpu_point ),
/*output [9:0] */ .oline2_fpga_point (jline2_fpga_point ),
/* */
/*input */ .iline3_en (jline3_en ),
/*input [20:0] */ .iline3_data_baseadrs (jline3_data_baseadrs ),
/*input [20:0] */ .iline3_mesg_baseadrs (jline3_mesg_baseadrs ),
/*input [20:0] */ .iline3_fpgawr_point_baseadrs (jline3_fpgawr_point_baseadrs),
/*input [1:0] */ .iline3_depth_define (jline3_depth_define ),
/*input [7:0] */ .iline3_mesg_toutcfg (jline3_mesg_toutcfg ),
/*input [9:0] */ .iline3_cpu_point (jline3_cpu_point ),
/*output [9:0] */ .oline3_fpga_point (jline3_fpga_point ),
/* */
/*input */ .iline4_en (jline4_en ),
/*input [20:0] */ .iline4_data_baseadrs (jline4_data_baseadrs ),
/*input [20:0] */ .iline4_mesg_baseadrs (jline4_mesg_baseadrs ),
/*input [20:0] */ .iline4_fpgawr_point_baseadrs (jline4_fpgawr_point_baseadrs),
/*input [1:0] */ .iline4_depth_define (jline4_depth_define ),
/*input [7:0] */ .iline4_mesg_toutcfg (jline4_mesg_toutcfg ),
/*input [9:0] */ .iline4_cpu_point (jline4_cpu_point ),
/*output [9:0] */ .oline4_fpga_point (jline4_fpga_point ),
/*//debug */
/*output reg [31:0]*/ .dma_pulse (jdma_pulse),
/*output reg [31:0]*/ .dma_state (jdma_state)
);
transform_8b_64b transform_8b_64b (
//system
/*input */ .sys_clk (sys_clk ),
/*input */ .sys_rst (sys_rst ),
/* */
/*//======up stream */
/*//dma_ctrl */
/*output reg [71:0] */ .recomb_data_2sw (recomb_data_2sw ),
/*output reg [71:0] */ .recomb_data_2host (recomb_data_2host ),
/*output reg [71:0] */ .recomb_data_2arm (recomb_data_2arm ),
/*output reg */ .recomb_den_2sw (recomb_den_2sw ),
/*output reg */ .recomb_den_2host (recomb_den_2host ),
/*output reg */ .recomb_den_2arm (recomb_den_2arm ),
/* */
/*//monitor data */
/*input [08:0] */ .host2sw_datain (host2sw_datain ),
/*input [08:0] */ .sw2host_datain (sw2host_datain ),
/*input [08:0] */ .sw2arm_datain ((DFT_mode==2'b11)?host2sw_datain:sw2arm_datain ),
/*input */ .host2sw_wen (1'b0),//(host2sw_wen ),
/*input */ .sw2host_wen (1'b0),//(sw2host_wen ),
/*input */ .sw2arm_wen ((DFT_mode==2'b11)?host2sw_wen:sw2arm_wen ),
/* */
/*//====down stream */
/*//send to ge port */
/*input [71:0] */ .down_data (down_data ),
/*input */ .down_den_H (down_den_H ),
/*input */ .down_den_L (down_den_L ),
/*output reg */ .down_buf_ready_H (down_buf_ready_H ),
/*output reg */ .down_buf_ready_L (down_buf_ready_L ),
/* */
/*//down */
/*output reg [8:0] */ .user_h_rx_datain (user_h_rx_datain ),
/*output reg */ .user_h_rx_wen (user_h_rx_wen ),
/*input */ .user_h_rx_ready (user_h_rx_ready ),
/* */
/*output reg [8:0] */ .user_l_rx_datain (user_l_rx_datain ),
/*output reg */ .user_l_rx_wen (user_l_rx_wen ),
/*input */ .user_l_rx_ready ((DFT_mode[0])?sw2host_tx_ready:user_l_rx_ready )
);
//=================================================
// bridge
//=================================================
bridge_sw2host bridge_sw2host (
//system
/*input */ .sys_clk (sys_clk),
/*input */ .sys_rst (sys_rst),
//sw side
/*input [7:0] */ .sw_user_rx_datain (sw_user_rx_datain),
/*input */ .sw_user_rx_eop (sw_user_rx_eop ),
/*input */ .sw_user_rx_err (sw_user_rx_err ),
/*input */ .sw_user_rx_wen (sw_user_rx_wen ),
/*output */ .sw_user_rx_ready (sw_user_rx_ready ),
//host side
/*output [8:0] */ .user_sw2arm_datain (sw2arm_datain),
/*output */ .user_sw2arm_wen (sw2arm_wen),
/* */
/*output [8:0] */ .user_sw2host_datain(sw2host_datain),
/*output */ .user_sw2host_wen (sw2host_wen),
/*input */ .user_sw2host_ready ((DFT_mode[0])?1'b1:sw2host_tx_ready),
//reg
/*input [47:0] */ .arm_mac (arm_mac),
/* */
/*//debug */
/*output reg [5:0] */ .bridge_sw2host_pulse (jbridge_sw2host_pulse)
);
bridge_host2sw bridge_host2sw (
//system
/*input */ .sys_clk (sys_clk),
/*input */ .sys_rst (sys_rst),
//host side
/*input [7:0] */ .user_h_rx_datain (user_h_rx_datain[7:0]),
/*input */ .user_h_rx_eop (user_h_rx_datain[8]),
/*input */ .user_h_rx_err (1'b0),
/*input */ .user_h_rx_wen (user_h_rx_wen),
/*output */ .user_h_rx_ready (user_h_rx_ready),
/* */
/*input [7:0] */ .user_m_rx_datain (host2sw_datain[7:0]),
/*input */ .user_m_rx_eop (host2sw_datain[8]),
/*input */ .user_m_rx_err (host2sw_werr),
/*input */ .user_m_rx_wen ((DFT_mode[0])?1'b0:host2sw_wen),
/*output */ .user_m_rx_ready (user_m_rx_ready),
/* */
/*input [7:0] */ .user_l_rx_datain (user_l_rx_datain[7:0]),
/*input */ .user_l_rx_eop (user_l_rx_datain[8]),
/*input */ .user_l_rx_err (1'b0),
/*input */ .user_l_rx_wen ((DFT_mode[0])?1'b0:user_l_rx_wen),
/*output */ .user_l_rx_ready (user_l_rx_ready),
//sw side
/*output reg [8:0] */ .user_tx_datain (sw_user_tx_datain),
/*output reg */ .user_tx_wen (sw_user_tx_wen ),
/*input */ .user_tx_ready (sw_user_tx_ready ),
/* */
/*//debug */
/*output reg [7:0] */ .bridge_host2sw_pulse (jbridge_host2sw_pulse)
);
//=================================================
// mac interface
//=================================================
//wire dcm_locked;
wire gtx_clk_bufg;
wire refclk_bufg;
wire gtx_clk_out;
wire gtx_clk90_out;
tri_mode_ethernet_mac_0_example_design_clocks u_design_clocks(
// differential clock inputs
/* input */ .clk_in_p (sys_clk),
/* input */ .clk_in_n (1'b0),
// asynchronous control/resets
/* input */ .glbl_rst (sys_rst),
/* output */ .dcm_locked (dcm_locked),
// clock outputs
/* output */ .gtx_clk_bufg (gtx_clk_bufg),
/* output */ .refclk_bufg (refclk_bufg),
/* output */ .s_axi_aclk ()
);
tri_mode_ethernet_mac_0_support u_0_support
(
/* input */ .gtx_clk (gtx_clk_bufg),
/* output */ .gtx_clk_out (gtx_clk_out ),
/* output */ .gtx_clk90_out (gtx_clk90_out),
// Reference clock for IDELAYCTRL's
/* input */ .refclk (refclk_bufg),
// asynchronous reset
/* input */ .glbl_rstn (dcm_locked)
);
eth_top eth_top_host (
//cfg if
/*input */ .clk_cbus (cbus_clk),
/*input */ .rst_cbus (cbus_rst),
/*input */ .ilbus_req (jlbus_req_p0),
/*input */ .ilbus_rw (jlbus_rw),
/*input [15:0] */ .ilbus_addr (jlbus_addr),
/*input [31:0] */ .ilbus_wdata (jlbus_wdata),
/*output */ .olbus_ack (jlbus_ack_p0),
/*output [31:0] */ .olbus_rdata (jlbus_rdata_p0),
/*input */ .eth_sys_loop (eth_host_sys_loop),
/*input */ .eth_line_loop (eth_host_line_loop),
/*input */ .selftest_flag (host_selftest_flag),
/*output reg [7:0] */ .self_check_err (host_self_check_err),
//user if
/*input */ .sys_clk (sys_clk ),
/*input */ .sys_rst (sys_rst ),
/*output [7:0] */ .user_rx_wdata (host2sw_datain[7:0]),
/*output */ .user_rx_weop (host2sw_datain[8]),
/*output */ .user_rx_werr (host2sw_werr),
/*output */ .user_rx_wen (host2sw_wen),
/* */
/*input [8:0] */ .user_tx_datain ((DFT_mode[0])?user_l_rx_datain:sw2host_datain),
/*input */ .user_tx_wen ((DFT_mode[0])?user_l_rx_wen:sw2host_wen),
/*output */ .user_tx_ready (sw2host_tx_ready),
//mac pin
/*input */ .gtx_clk (gtx_clk_out ),
/*input */ .gtx_clk90 (gtx_clk90_out ),
/*input */ .glbl_rstn (dcm_locked ),
/*output [3:0] */ .rgmii_txd (host_rgmii_txd ),
/*output */ .rgmii_tx_ctl (host_rgmii_tx_ctl ),
/*output */ .rgmii_txc (host_rgmii_txc ),
/*input [3:0] */ .rgmii_rxd (host_rgmii_rxd ),
/*input */ .rgmii_rx_ctl (host_rgmii_rx_ctl ),
/*input */ .rgmii_rxc (host_rgmii_rxc ),
/*inout */ .mdio (host_mdio ),
/*output */ .mdc (host_mdc ),
/*//debug */
/*output reg [2:0] */ .eth_user_pls (host_eth_user_pls )
);
eth_top eth_top_sw (
//cfg if
/*input */ .clk_cbus (cbus_clk),
/*input */ .rst_cbus (cbus_rst),
/*input */ .ilbus_req (jlbus_req_p1),
/*input */ .ilbus_rw (jlbus_rw),
/*input [15:0] */ .ilbus_addr (jlbus_addr),
/*input [31:0] */ .ilbus_wdata (jlbus_wdata),
/*output */ .olbus_ack (jlbus_ack_p1),
/*output [31:0] */ .olbus_rdata (jlbus_rdata_p1),
/*input */ .eth_sys_loop (eth_sw_sys_loop),
/*input */ .eth_line_loop (eth_sw_line_loop),
/*input */ .selftest_flag (sw_selftest_flag),
/*output reg [7:0] */ .self_check_err (sw_self_check_err),
//user if
/*input */ .sys_clk (sys_clk ),
/*input */ .sys_rst (sys_rst ),
/*output [7:0] */ .user_rx_wdata (sw_user_rx_datain),
/*output */ .user_rx_weop (sw_user_rx_eop ),
/*output */ .user_rx_werr (sw_user_rx_err ),
/*output */ .user_rx_wen (sw_user_rx_wen ),
/* */
/*input [8:0] */ .user_tx_datain (sw_user_tx_datain),
/*input */ .user_tx_wen (sw_user_tx_wen ),
/*output */ .user_tx_ready (sw_user_tx_ready ),
//mac pin
/*input */ .gtx_clk (gtx_clk_out ),
/*input */ .gtx_clk90 (gtx_clk90_out ),
/*input */ .glbl_rstn (dcm_locked ),
/*output [3:0] */ .rgmii_txd (sw_rgmii_txd ),
/*output */ .rgmii_tx_ctl (sw_rgmii_tx_ctl ),
/*output */ .rgmii_txc (sw_rgmii_txc ),
/*input [3:0] */ .rgmii_rxd (sw_rgmii_rxd ),
/*input */ .rgmii_rx_ctl (sw_rgmii_rx_ctl ),
/*input */ .rgmii_rxc (sw_rgmii_rxc ),
/*inout */ .mdio (sw_mdio ),
/*output */ .mdc (sw_mdc ),
/*//debug */
/*output reg [2:0] */ .eth_user_pls (sw_eth_user_pls )
);
// User logic end
assign PORT0_LED_ACT = 1'b1;
assign PORT0_LED_LINK = ~PHY_PORT0_LED2;
assign PORT1_LED_ACT = 1'b1;
assign PORT1_LED_LINK = ~PHY_PORT1_LED2;
monitor_cnt u_host_monitor_cnt (
//cbus
/*input */ .clk_cbus (cbus_clk),
/*input */ .rst_cbus (cbus_rst),
/*input */ .ilbus_req (jlbus_req_p2),
/*input */ .ilbus_rw (jlbus_rw),
/*input [15:0] */ .ilbus_addr (jlbus_addr),
/*input [31:0] */ .ilbus_wdata (jlbus_wdata),
/*output */ .olbus_ack (jlbus_ack_p2),
/*output [31:0] */ .olbus_rdata (jlbus_rdata_p2),
/*//ext */
/*input */ .ilbus_req_ext (jlbus_req_p3),
/*output */ .olbus_ack_ext (jlbus_ack_p3),
/*output [31:0] */ .olbus_rdata_ext(jlbus_rdata_p3),
/*//debug */
/*output [11:0] */ .table3_cnt_inused (table3_cnt_inused ),
/*output [11:0] */ .table3_cnt_pushout (table3_cnt_pushout),
/*output [11:0] */ .table5_cnt_inused (table5_cnt_inused ),
/*output [11:0] */ .table5_cnt_pushout (table5_cnt_pushout),
/*//user */
/*input */ .sys_clk (sys_clk ),
/*input */ .sys_rst (sys_rst ),
/*input [8:0] */ .up_din (host2sw_datain),
/*input */ .up_din_err (host2sw_werr),
/*input */ .up_din_wen (host2sw_wen),
/*input [8:0] */ .dn_din ((DFT_mode[0])?user_l_rx_datain:sw2host_datain),
/*input */ .dn_din_err (1'b0),
/*input */ .dn_din_wen ((DFT_mode[0])?user_l_rx_wen:sw2host_wen)
);
/*
//reg output_flag;
//
test test_u0(
//system
.sys_clk (sys_clk),
.sys_rst (sys_rst),
.output_flag (output_flag_u0)
);
test test_u1(
//system
.sys_clk (sys_clk),
.sys_rst (sys_rst),
.output_flag (output_flag_u1)
);
test test_u2(
//system
.sys_clk (sys_clk),
.sys_rst (sys_rst),
.output_flag (output_flag_u2)
);
test test_u3(
//system
.sys_clk (sys_clk),
.sys_rst (sys_rst),
.output_flag (output_flag_u3)
);
*/
endmodule