基于FPGA数字式竞赛抢答器
部分报告
完整版点这里
各个模块代码
//////////////////////////////////////*顶层模块*//////////////////////////////////////////////////
module qiangdaqi_top_1(rst, clk, s0, s1, s2,clr, add, sub,fmq_out,led_out,sel,A,B,C,D,E,F,G,H
);
input rst;
input clk;
input s0;
input s1;
input s2;
input clr;
input add;
input sub;
output [2:0] led_out;
output fmq_out;
output [2:0] sel;
output A,B,C,D,E,F,G,H;
wire [2:0] chose;
wire [7:0] a1;
wire [7:0] a2;
wire [7:0] a3;
wire [3:0] daout;
qd_zz qd_zz_1 (
.rst(rst),
.clk(clk),
.s0(s0),
.s1(s1),
.s2(s2),
.chose(chose));
jf_zz jf_zz_1 (
.clr(clr),
.add(add),
.sub(sub),
.chose(chose),
.a1(a1),
.a2(a2),
.a3(a3)
);
fmq_zz fmq_zz_1 (
.chose(chose),
.rst(rst),
.fmq_out(fmq_out),
.clk(clk),
.led_out(led_out)
);
dtsm_zz dtsm_zz_1 (
.clk(clk),
.rst(rst),
.a1(a1),
.a2(a2),
.a3(a3),
.daout(daout),
.sel(sel)
);
ym_zz ym_zz_1 (
.daout(daout),
.A(A),
.B(B),
.C(C),
.D(D),
.E(E),
.F(F),
.G(G),
.H(H)
);
endmodule
///////////////////////////////////*抢答鉴别模块*//////////////////////////////////////////////
module qd_zz(rst, clk, s0, s1, s2, chose
);
input rst;
input clk;
input s0;
input s1;
input s2;
output [2:0] chose;
reg [2:0] chose;
always @(negedge rst or posedge clk)
begin
if (!rst)
begin
chose <= 3'b000;
end
else
begin
if ((s0 == 1'b1 | chose[0] == 1'b1) & (~(chose[1] == 1'b1 | chose[2] == 1'b1 )))
begin
chose[0] <= 1'b1;
end
if ((s1 == 1'b1 | chose[1] == 1'b1) & (~(chose[0] == 1'b1 | chose[2] == 1'b1 )))
begin
chose[1] <= 1'b1;
end
if ((s2 == 1'b1 | chose[2] == 1'b1) & (~(chose[1] == 1'b1 | chose[0] == 1'b1 )))
begin
chose[2] <= 1'b1;
end
end
end
endmodule
//////////////////////////////////////*计分模块*////////////////////////////////////////////
module jf_zz(clr, add, sub, chose, a1, a2, a3,led_out
);
input clr;
input add;
input sub;
input [2:0] chose;
output [7:0] a1;
reg [7:0] a1;
output [7:0] a2;
reg [7:0] a2;
output [7:0] a3;
reg [7:0] a3;
output [2:0] led_out;
wire jiajian;
assign jiajian=add^sub;
assign led_out = chose;
always @(posedge clr or posedge jiajian)
if (clr == 1'b1)
begin
a1 <= 8'b00010000;
a2 <= 8'b00010000;
a3 <= 8'b00010000;
end
else
begin
if (add == 1'b1)
case (chose)
3'b001 :
if (a1 == 8'b00100000)
;
else if (a1[3:0] == 4'b1001)
begin
a1[3:0] <= 4'b0000;
a1[7:4] <= a1[7:4] + 1'b1;
end
else
a1[3:0] <= a1[3:0] + 1'b1;
3'b010 :
if (a2 == 8'b00100000)
;
else if (a2[3:0] == 4'b1001)
begin
a2[3:0] <= 4'b0000;
a2[7:4] <= a2[7:4] + 1'b1;
end
else
a2[3:0] <= a2[3:0] + 1'b1;
3'b100 :
if (a3 == 8'b00100000)
;
else if (a3[3:0] == 4'b1001)
begin
a3[3:0] <= 4'b0000;
a3[7:4] <= a3[7:4] + 1'b1;
end
else
a3[3:0] <= a3[3:0] + 1'b1;
default :
;
endcase
else if (sub == 1'b1)
case (chose)
3'b001 :
if (a1 == 8'b00000000)
;
else if (a1[3:0] == 4'b0000)
begin
a1[3:0] <= 4'b1001;
a1[7:4] <= a1[7:4] - 1'b1;
end
else
a1[3:0] <= a1[3:0] - 1'b1;
3'b010 :
if (a2 == 8'b00000000)
;
else if (a2[3:0] == 4'b0000)
begin
a2[3:0] <= 4'b1001;
a2[7:4] <= a2[7:4] - 1'b1;
end
else
a2[3:0] <= a2[3:0] - 1'b1;
3'b100 :
if (a3 == 8'b00000000)
;
else if (a3[3:0] == 4'b0000)
begin
a3[3:0] <= 4'b1001;
a3[7:4] <= a3[7:4] - 1'b1;
end
else
a3[3:0] <= a3[3:0] - 1'b1;
default :
;
endcase
end
endmodule
/////////////////////////////////////*蜂鸣器和led*/////////////////////////////////////////////
module fmq_zz(chose,rst,fmq_out,led_out,clk);
input rst,clk;
input [2:0]chose;
output [2:0]led_out;
output fmq_out;
reg fmq_out,clk1s;
reg [27:0] count1s;
wire ena;
assign led_out=chose;
always@(posedge clk or negedge rst)
begin
if(!rst)
begin
count1s=28'd0; clk1s=1'd0;
end
else
begin
if(count1s>28'd20)
begin
count1s=28'd0;
clk1s=~clk1s;
end
else
count1s=count1s+1'd1;
end
end
assign ena=chose[0]|chose[1]|chose[2];
reg [2:0]count3;
always@(posedge clk1s or negedge rst)
begin
if(!rst)
count3=3'd0;
else
if(ena)
count3=count3+1'd1;
else
count3=0;
end
always@(posedge clk)
begin
case(count3)
3'b000: fmq_out=1'b0;//count3默认是000，所以这样
3'b001: fmq_out=1'b1;//001，010，011时，输出高
3'b010: fmq_out=1'b1;
3'b011: fmq_out=1'b1;
3'b100: fmq_out=1'b0;
3'b101: fmq_out=1'b0;
3'b110: fmq_out=1'b0;
default:fmq_out=1'b0;
endcase
end
endmodule
///////////////////////////////////*动态扫描*///////////////////////////////////////////////
module dtsm_zz(clk,rst, a1,a2,a3, daout, sel);
input rst;
input clk;
input [7:0] a1;
input [7:0] a2;
input [7:0] a3;
output [3:0] daout;
reg [3:0] daout;
output [2:0] sel;
reg [2:0] sec;
always @(posedge clk or negedge rst)
begin
if(!rst)
begin
sec<=3'b000;
end
else
if (sec == 3'b101)
sec <= 3'b000;
else
sec <= sec + 1;
end
always @(*)
case (sec)
3'b000 :
daout <= a1[7:4];
3'b001 :
daout <= a1[3:0];
3'b010 :
daout <= a2[7:4];
3'b011 :
daout <= a2[3:0];
3'b100 :
daout <= a3[7:4];
3'b101 :
daout <= a3[3:0];
default :
daout <= 4'b0000;
endcase
assign sel = sec;
endmodule
////////////////////////////////////*译码模块*//////////////////////////////////////////////
module ym_zz(daout, A, B, C, D, E, F, G, H
);
input [3:0] daout;
output A;
output B;
output C;
output D;
output E;
output F;
output G;
output H;
wire [3:0] DATA;
reg [7:0] DOUT;
assign DATA = daout;
always @(DATA)
case (DATA)
4'b0000 :
DOUT <= 8'b11000000;
4'b0001 :
DOUT <= 8'b11111001;
4'b0010 :
DOUT <= 8'b10100110;
4'b0011 :
DOUT <= 8'b10110000;
4'b0100 :
DOUT <= 8'b10011001;
4'b0101 :
DOUT <= 8'b10010010;
4'b0110 :
DOUT <= 8'b10000010;
4'b0111 :
DOUT <= 8'b11111000;
4'b1000 :
DOUT <= 8'b10000000;
4'b1001 :
DOUT <= 8'b10010000;
default :
DOUT <= 8'b11000000;
endcase
assign H = DOUT[7];
assign G = DOUT[6];
assign F = DOUT[5];
assign E = DOUT[4];
assign D = DOUT[3];
assign C = DOUT[2];
assign B = DOUT[1];
assign A = DOUT[0];
endmodule
欢迎指正