FPGA学习笔记8--模60BCD码计数器

module count60(
input clk,
input cin,
input reset,
input load,
input [7:0]data,
output reg [7:0]qout,
output cout
);
always @(posedge clk or negedge reset)begin
    if(!reset)
    qout<=0;
    else if(load)
    qout<=data;
    else if(cin)
        begin
            if(qout[3:0]==9)
                begin
                    qout[3:0]<=0;
                    if(qout[7:4]==5)
                        qout[7:4]<=0;
                     else qout[7:4]<=qout[7:4]+1'b1;   
                end
                
            else qout[3:0]<= qout[3:0]+1'b1;
        end
end
assign cout=((qout==8'h59)&cin)?1:0;
endmodule

`timescale 1ns / 1ns
module tb_counter60(
    );
    reg  [7:0]data;
    reg  load,cin,clk,reset;
    wire cout;
    wire [7:0] qout;
    count60 u1(.data(data),.load(load),.clk(clk),.cin(cin),.reset(reset),.qout(qout),.cout(cout));
    initial begin
    reset<=1'b0;
    load<=1'b1;
    data<=8'b00001111;
    cin<=1'b1;
    clk<=1'b0;
    #100 reset<=1'b1;
    #100 load <=1'b0;
    #5000 $finish;
    end
    always begin
    #10 clk<=~clk;
    end
endmodule