fpga与三八译码器(BASYS3 VIVADO18)

参考这篇文章

• 之前写过如何创建项目，看这里，现在稍作补充
• 在SYNTHESIS下打开Schematic
  
• 就和?了
  
• decoder.v

module decoder(
    input [2:0] sw,
    output reg[7:0] led
    );
    always@(sw)begin
        case(sw)
            3'b000: led = 8'b0000_0001;
            3'b001: led = 8'b0000_0010;
            3'b010: led = 8'b0000_0100;
            3'b011: led = 8'b0000_1000;
            3'b100: led = 8'b0001_0000;
            3'b101: led = 8'b0010_0000;
            3'b110: led = 8'b0100_0000;
            3'b111: led = 8'b1000_0000;
        endcase
    end
endmodule

• decoder.xdc

#switches
set_property PACKAGE_PIN V17 [get_ports {sw[0]}]
    set_property IOSTANDARD LVCOMS33 [get_ports {sw[0]}]
set_property PACKAGE_PIN V16 [get_ports {sw[1]}]
    set_property IOSTANDARD LVCOMS33 [get_ports {sw[1]}]
set_property PACKAGE_PIN W16 [get_ports {sw[2]}]
    set_property IOSTANDARD LVCOMS33 [get_ports {sw[2]}]

#LEDS
set_property PACKAGE_PIN U16 [get_ports {led[0]}]
    set_property IOSTANDARD LVCOMS33 [get_ports {led[0]}]
set_property PACKAGE_PIN E19 [get_ports {led[1]}]
    set_property IOSTANDARD LVCOMS33 [get_ports {led[1]}]
set_property PACKAGE_PIN U19 [get_ports {led[2]}]
    set_property IOSTANDARD LVCOMS33 [get_ports {led[2]}]
set_property PACKAGE_PIN V19 [get_ports {led[3]}]
    set_property IOSTANDARD LVCOMS33 [get_ports {led[3]}]
set_property PACKAGE_PIN W18 [get_ports {led[4]}]
    set_property IOSTANDARD LVCOMS33 [get_ports {led[4]}]
set_property PACKAGE_PIN U15 [get_ports {led[5]}]
    set_property IOSTANDARD LVCOMS33 [get_ports {led[5]}]
set_property PACKAGE_PIN U14 [get_ports {led[6]}]
    set_property IOSTANDARD LVCOMS33 [get_ports {led[6]}]
set_property PACKAGE_PIN V14 [get_ports {led[7]}]
    set_property IOSTANDARD LVCOMS33 [get_ports {led[7]}]

• 不知道为什么报错
  
• 学长说IO配得不太对
  
• 在RTL修改
  
• 左边也可以连接器件，要是没有弹出消息的话
  
• 写入flash
  
  
• 烧写出现错误
  
  
• 换一台电脑烧写