arm64 el1_sync

/*  * EL1 mode handlers.  */  .align 6 el1_sync:  kernel_entry 1  msr daifclr, #1    //enable fiq  mrs x1, esr_el1   // read the syndrome register  lsr x24, x1, #ESR_EL1_EC_SHIFT // exception class  cmp x24, #ESR_EL1_EC_DABT_EL1 // data abort in EL1  b.eq el1_da  cmp x24, #ESR_EL1_EC_SYS64  // configurable trap  b.eq el1_undef  cmp x24, #ESR_EL1_EC_SP_ALIGN // stack alignment exception  b.eq el1_sp_pc  cmp x24, #ESR_EL1_EC_PC_ALIGN // pc alignment exception  b.eq el1_sp_pc  cmp x24, #ESR_EL1_EC_UNKNOWN // unknown exception in EL1  b.eq el1_undef  cmp x24, #ESR_EL1_EC_BREAKPT_EL1 // debug exception in EL1  b.ge el1_dbg  b el1_inv el1_da:  /*   * Data abort handling   */  mrs x0, far_el1  enable_dbg_if_not_stepping x2  // re-enable interrupts if they were enabled in the aborted context  tbnz x23, #7, 1f   // PSR_I_BIT  enable_irq 1:  mov x2, sp    // struct pt_regs  bl do_mem_abort

 // disable interrupts before pulling preserved data off the stack  disable_irq  kernel_exit 1 el1_sp_pc:  /*   * Stack or PC alignment exception handling   */  mrs x0, far_el1  mov x2, sp  b do_sp_pc_abort el1_undef:  /*   * Undefined instruction   */  mov x0, sp  b do_undefinstr el1_dbg:  /*   * Debug exception handling   */  cmp x24, #ESR_EL1_EC_BRK64  // if BRK64  cinc x24, x24, eq   // set bit '0'  tbz x24, #0, el1_inv  // EL1 only  mrs x0, far_el1  mov x2, sp    // struct pt_regs  bl do_debug_exception

 kernel_exit 1 el1_inv:  // TODO: add support for undefined instructions in kernel mode  mov x0, sp  mov x1, #BAD_SYNC  mrs x2, esr_el1  b bad_mode ENDPROC(el1_sync)