verilog语言设计有限状态机习题

module seqdet(x,z,clk,rst,state);

input x,clk,rst;

output z;

output[2:0] state;

reg[2:0] state;

wire z;

parameter IDLE='d0, A='d1, B='d2,

C='d3, D='d4,

E='d5;

assign z = ( state==D)? 1 : 0; //?x=0???????E?

//???D??x??1???

//???1????? state==E && x==0 ??

always @(posedge clk)

if(!rst)

begin

state <= IDLE;

end

else

casex(state)

IDLE : if(x==1)

begin

state <= A;

end

A:if(x==1)

begin

state <= B;

end

else

be