quartus Ⅱ 12.1 使用教程（7） vga显示测试

开发板使用的是EP4CE15F23C8，软件使用的是quartus 12.1 ，工程主要使用vga显示方格

行计数

//hsync计数
always@(posedge clk_148M or negedge i_rst_n)begin
		if(i_rst_n	==	1'b0)
			hsync_cnt	<=	12'd0;
		else	if(hsync_cnt == H_TOTAL -12'd1)
			hsync_cnt	<=	12'd0;
		else
			hsync_cnt	<=	hsync_cnt	+	1'b1;
end

场计数

//VSYNC计数
always@(posedge clk_148M or negedge	i_rst_n)begin
		if(i_rst_n	==	1'b0)
			vsync_cnt	<=	12'd0;
		else	if(hsync_cnt == H_TOTAL -12'd1)
			if(vsync_cnt == V_TOTAL - 12'd1)
				vsync_cnt	<=	12'd0;
			else
				vsync_cnt	<=	vsync_cnt	+	1'b1;
end

产生行信号

//hsync
assign vga_hs = ((hsync_cnt >= 12'd0)&&(hsync_cnt < H_SYNC))? 1'b0:1'b1;

产生场信号

//vsync
assign vga_vs = ((vsync_cnt >= 12'd0)&&(vsync_cnt < V_SYNC))? 1'b0:1'b1;

行场信号有效区域

//hsync和vsync显示有效区域
assign	hsync_en = ((hsync_cnt >= (H_SYNC + H_BACK))&&(hsync_cnt < (H_SYNC + H_BACK + H_ACTIVE)));
assign	vsync_en = ((vsync_cnt	>= (V_SYNC + V_BACK))&&(vsync_cnt < (V_SYNC + V_BACK + V_ACTIVE)));

输出显示

assign	vga_r	=	(hsync_en && vsync_en)? grid_data_1[15:11]: 5'd0;
assign	vga_g	=	(hsync_en && vsync_en)? grid_data_1[10:5]: 6'd0;
assign	vga_b	=	(hsync_en && vsync_en)? grid_data_1[4:0]: 5'd0;

下面的程序是显示一个1080p的一个方格的vga程序

module vga_test(
	i_clk,
	i_rst_n,
	vga_hs,
	vga_vs,
	vga_r,
	vga_g,
	vga_b

);

input				i_clk;
input				i_rst_n;
output			vga_hs;
output			vga_vs;
output	[4:0]	vga_r;
output	[5:0]	vga_g;
output	[4:0]	vga_b;




parameter H_SYNC = 12'd44;
parameter H_BACK = 12'd148;
parameter H_ACTIVE = 12'd1920;
parameter H_FRONT = 12'd88;
parameter H_TOTAL = H_SYNC + H_BACK + H_ACTIVE + H_FRONT;

parameter V_SYNC = 12'd5;
parameter V_BACK = 12'd36;
parameter V_ACTIVE = 12'd1080;
parameter V_FRONT = 12'd4;
parameter V_TOTAL = V_SYNC + V_BACK + V_ACTIVE + V_FRONT;


reg	[11:0]	hsync_cnt;
reg	[11:0]	vsync_cnt;
wire				hsync_en;
wire				vsync_en;
wire				clk_148M;
reg	[15:0] 	grid_data_1;
reg	[4:0]		vga_r_reg;
reg	[5:0]		vga_g_reg;
reg	[4:0]		vga_b_reg;



pll	pll_inst (
	.inclk0 ( i_clk ),//input	50M
	.c0 ( clk_148M )	//output	148M
	);

//HSYNC计数
always@(posedge clk_148M or negedge i_rst_n)begin
		if(i_rst_n	==	1'b0)
			hsync_cnt	<=	12'd0;
		else	if(hsync_cnt == H_TOTAL -12'd1)
			hsync_cnt	<=	12'd0;
		else
			hsync_cnt	<=	hsync_cnt	+	1'b1;
end

//hsync
assign vga_hs = ((hsync_cnt >= 12'd0)&&(hsync_cnt < H_SYNC))? 1'b0:1'b1;

//VSYNC计数
always@(posedge clk_148M or negedge	i_rst_n)begin
		if(i_rst_n	==	1'b0)
			vsync_cnt	<=	12'd0;
		else if(hsync_cnt == H_TOTAL -12'd1)
			if(vsync_cnt == V_TOTAL - 12'd1)
				vsync_cnt	<=	12'd0;
		else
			vsync_cnt	<=	vsync_cnt	+	1'b1;
end

//vsync
assign vga_vs = ((vsync_cnt >= 12'd0)&&(vsync_cnt < V_SYNC))? 1'b0:1'b1;

//hsync和vsync显示有效区域
assign	hsync_en	=	((hsync_cnt >= (H_SYNC + H_BACK))&&(hsync_cnt < (H_SYNC + H_BACK + H_ACTIVE)));
assign	vsync_en	=	((vsync_cnt	>=	(V_SYNC + V_BACK))&&(vsync_cnt < (V_SYNC + V_BACK + V_ACTIVE)));

//方格
 always@(posedge clk_148M or negedge i_rst_n)begin
            if(i_rst_n	==	1'b0)
				 grid_data_1<= 16'h0000;
            else if ((hsync_cnt[4]==1'b1) ^ (vsync_cnt[4]==1'b1))     //产生小格子图像
			    grid_data_1<= 16'h0000;
            else
			    grid_data_1<= 16'hffff;  
 end


assign	vga_r	=	(hsync_en && vsync_en)? grid_data_1[15:11]: 5'd0;
assign	vga_g	=	(hsync_en && vsync_en)? grid_data_1[10:5]: 6'd0;
assign	vga_b	=	(hsync_en && vsync_en)? grid_data_1[4:0]: 5'd0;



endmodule

			

显示效果如下图