用VHDL语言实现任意奇数分频，代码如下：

用VHDL语言实现任意奇数分频，代码如下：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL; 
use IEEE.STD_LOGIC_ARITH.ALL; 

entity Odiv_freq is
generic(
	num_div : integer
	);
port( 
	clk     : in std_logic;
	reset   : in std_logic;
	div_clk : out std_logic
	);
end Odiv_freq;
architecture Odiv_freq of Odiv_freq is

signal count : integer range 0 to num_div-1;
signal s1    : std_logic := '0';
signal s2    : std_logic := '0';

begin
	process(clk, reset)
	begin
		if(reset = '1') then
			count <= 0;
			s1    <= '1';
			s2    <= '1';
		elsif (clk'event and clk = '1') then
			if (count = 0) then
				count <= num_div-1;
				s1    <= not s1;
			else
				count <= count - 1;
				s1    <= s1;
			end if;
		elsif (clk'event and clk = '0') then 
			if (count = (num_div-1)/2) then
				s2    <= not s2;
			else
				s2    <= s2;
			end if;
		end if;			
	end process;
	
	div_clk <= s1 xor s2;
	
end Odiv_freq;