DC综合的脚本总结

#step 1Read&elaborate the RTL file list & check
#==========================================================
set TOP_MODULE spi
analyze -format verilog  [list spi.v serial_parallel.v switch.v]
elaborate $TOP_MODULE  -architecture verilog
current_design $TOP_MODULE
if {[Link] == 0} {
     echo Link with error!;
      exit;
}
if {[check_design] == 0} {
     echo check design with error! ;
      exit;
}
#step 2 reset the design first
#===========================================================
reset_design 
#===========================================================
#step 3 write the unmapped ddc file 
#===========================================================
uniquify
set uniquify_naming_style %s_%d
set UNMAPPED_PATH  .unmapped
write -f ddc -hierarchy -output ${UNMAPPED_PATH}${TOP_MODULE}.ddc
#===========================================================
#step 4Defined clock
#===========================================================
set CLK_NAME      SCLK
set CLK_PERIOD    20
set CLK_SKEW      [expr $CLK_PERIOD0.05]
set CLK_TRAN      [expr $CLK_PERIOD0.01]
set CLK_SRC_LATENCY  [expr $CLK_PERIOD0.1]
set CLK_LATENCY   [expr $CLK_PERIOD0.1]
create_clock -period $CLK_PERIOD  [get_ports $CLK_NAME]
set_ideal_network      [get_ports $CLK_NAME]
set_dont_touch_network [get_ports $CLK_NAME]
set_drive  0           [get_ports $CLK_NAME]
set_clock_uncertainty     -setup $CLK_SKEW       [get_ports $CLK_NAME]
set_clock_transition      -max   $CLK_TRAN       [get_ports $CLK_NAME]
set_clock_latency -source -max $CLK_SRC_LATENCY  [get_ports $CLK_NAME]
set_clock_latency         -max $CLK_LATENCY      [get_ports $CLK_NAME]
#=============================================================
#step 5Define reset
#=============================================================
set RST_NAME    CSB
set_ideal_network [get_ports $RST_NAME]
set_dont_touch_network [get_ports $RST_NAME]
set_drive  0           [get_ports $RST_NAME]
#=============================================================
#step 6set input delay
#============================================================
set ALL_IN_EXCEPT_CLK [remove_from_collection [all_inputs]  [get_ports $CLK_NAME]]
set INPUT_DELAY       [expr $CLK_PERIOD0.5]
set_input_delay    $INPUT_DELAY     -clock $CLK_NAME    $ALL_IN_EXCEPT_CLK  
#=============================================================
#step 7set output delay
#=============================================================
set   LIB_NAME          tcbn65gplustc
set   OPERA_CONDITION   NCCOM
set   OUTPUT_DELAY   [expr $CLK_PERIOD0.4]
set   MAX_LOAD       [expr [load_of $LIB_NAMEBUFFD3BWP7TZ]10]
set_output_delay   -max  $OUTPUT_DELAY   -clock $CLK_NAME [all_outputs]
set_output_delay   -min  [expr $OUTPUT_DELAY0.1]   -clock $CLK_NAME [all_outputs]
set_load             [expr $MAX_LOAD1]   [all_outputs]
set_isolate_ports    -type buffer         [all_outputs]
#==============================================================
#===========================================================
#step 8 set_operating_conditions & wore_load model
#==========================================================
set_operating_conditions    -max $OPERA_CONDITION 
                            -max_library $LIB_NAME
set   auto_wire_load_selection  false
set_wire_load_mode top
#============================================================
#step 9set area
#============================================================
set_max_area 0
#============================================================
#step 10wite post_process files
#=============================================================
set compile_automatic_clock_phase_inference relaxed
set compile_seqmap_propagate_constants false
#============================================================
#step 11set group path 
#avoid getting stack on one path
#=============================================================
group_path  -name $CLK_NAME  -weight 5                            -critical_range [expr $CLK_PERIOD0.1]
group_path  -name INPUTS   -from [all_inputs]                     -critical_range [expr $CLK_PERIOD0.1]
group_path  -name OUTPUTS  -to [all_outputs]                      -critical_range [expr $CLK_PERIOD0.1]
group_path  -name COMB     -from [all_inputs]  -to [all_outputs]  -critical_range [expr $CLK_PERIOD0.1]
report_path_group
#==============================================================
#step 12compile flow
#=============================================================
compile -map_effort high -area_effort high -boundary_optimization 
#=============================================================
#step 11wirte post_process files
#==============================================================
write -format verilog -hierarchy -output .outputsspi.v
write -format ddc -hier -o .outputsspi.ddc
write_sdc .outputsspi.sdc
write_sdf .outputsspi.sdf
#==============================================================
#step 12generate report files
#==============================================================
report_timing -delay max  .reportsspi_setup_rt.rpt
report_timing -delay min  .reportsspi_hold_rt.rpt
report_constraint -verbose  .reportsspi_rc.rpt


#write_sdf .outputsskyworks_v7.sdf#