EDA数字钟设计（verilog）——显示译码模块

        进行正常的示数和闹钟的示数，利用电路的共阳极数码管的特性进行10个数字和“-”的译码，分别利用两位16进制进行定义，更加简约方便，闹钟电路和正常示数分开显示，防止优先级之间的干扰，动态显示电路的频率为1KHz，超过了人眼可以分辨出来的频率。利用除法和求余进行个位和十位的提取，使代码变得简单易懂。具体代码如下：

module xianshi(clk_1KHz,second,minute,hour,choice,dianliang,hour_reg,min_reg,naozhong_swh,swh,baochi_swh);

input [5:0]second,minute,hour;
input [5:0]hour_reg,min_reg;
input clk_1KHz;
input naozhong_swh,baochi_swh;
input [1:0]swh;
reg [3:0]sec_ge,sec_shi,hour_ge,hour_shi,min_ge,min_shi;
reg [3:0]scan;
reg [7:0]data;
output reg[7:0]choice;
output reg[7:0]dianliang;

always@(posedge clk_1KHz) //扫描电路
	begin
		if(scan == 'b111)
			scan <= 'b000;
		else
			scan <= scan + 'd1;
	end

always@(clk_1KHz)  //时分秒个位十位提取
	begin
		if((naozhong_swh)&&(swh[1:0] == 'b11)&&(!baochi_swh))
			begin
				min_ge <= min_reg%10;
				min_shi <= min_reg/10;
				hour_ge <= hour_reg%10;
				hour_shi <= hour_reg/10;
				sec_ge <= 'd0;
				sec_shi <= 'd0;
				case(scan)
					'b000:
						begin
							choice <= 'b11111110;
							data <= sec_ge;
						end
					'b001:
						begin
							choice <= 'b11111101;
							data <= sec_shi;
						end
					'b010:
						begin
							choice <= 'b11111011;
							data <= 'd10;
						end
					'b011:
						begin
							choice <= 'b11110111;
							data <= min_ge;
						end
					'b100:
						begin
							choice <= 'b11101111;
							data <= min_shi;
						end
					'b101:
						begin
							choice <= 'b11011111;
							data <= 'd10;
						end
					'b110:
						begin
							choice <= 'b10111111;
							data <= hour_ge;
						end
					'b111:
						begin
							choice <= 'b01111111;
							data <= hour_shi;
						end
					default:
						begin
							choice <= 'b00000000;
							data <= 'd5;
						end
				endcase
			end
		else
			begin
				sec_ge <= second%10;
				sec_shi <= second/10;
				min_ge <= minute%10;
				min_shi <= minute/10;
				hour_ge <= hour%10;
				hour_shi <= hour/10;
				case(scan)
					'b000:
						begin
							choice <= 'b11111110;
							data <= sec_ge;
						end
					'b001:
						begin
							choice <= 'b11111101;
							data <= sec_shi;
						end
					'b010:
						begin
							choice <= 'b11111011;
							data <= 'd10;
						end
					'b011:
						begin
							choice <= 'b11110111;
							data <= min_ge;
						end
					'b100:
						begin
							choice <= 'b11101111;
							data <= min_shi;
						end
					'b101:
						begin
							choice <= 'b11011111;
							data <= 'd10;
						end
					'b110:
						begin
							choice <= 'b10111111;
							data <= hour_ge;
						end
					'b111:
						begin
							choice <= 'b01111111;
							data <= hour_shi;
						end
					default:
						begin
							choice <= 'b00000000;
							data <= 'd0;
						end
				endcase
			end
		case(data)
			'd0:dianliang = 'hc0;
			'd1:dianliang = 'hf9;
			'd2:dianliang = 'ha4;
			'd3:dianliang = 'hb0;
			'd4:dianliang = 'h99;
			'd5:dianliang = 'h92;
			'd6:dianliang = 'h82;
			'd7:dianliang = 'hf8;
			'd8:dianliang = 'h80;
			'd9:dianliang = 'h90;
			'd10:dianliang = 'hbf;
		endcase
	end
	
endmodule

封装图如下：