SOC设计之APB接口的简易SRAM

module apb_sram
#(
parameter DATA_WIDTH=5'd16,
parameter DATA_DEPTH=3'd5,
parameter ADDR_WIDTH=7'd32
 )
(
input		PCLK,
input		PSEL,
input		PENABLE,
input		PWRITE,
input		[DATA_WIDTH-1:0] PWDATA,
input		[ADDR_WIDTH-1:0] PADDR,
input		PRESETn,
output		CEN,
output		reg [DATA_WIDTH-1:0] PRDATA
 );

integer i;
reg [DATA_WIDTH-1:0] SRAM [DATA_DEPTH-1:0];//二维数组定义

assign CEN=PSEL&&PENABLE;//片??信?

always@(posedge PCLK or negedge PRESETn)
begin
	if(!PRESETn)
	begin //SRAN复位，内部清?
		for(i=0;i

tb:
 

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2020/07/02 21:17:32
// Design Name: 
// Module Name: apb_sram_test
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


module apb_sram_test;
parameter DATA_WIDTH=5'd16;
parameter DATA_DEPTH=3'd5;
parameter ADDR_WIDTH=7'd32;
reg PCLK;
reg PSEL;
reg PWRITE;
reg PENABLE;
reg PRESETn;
reg [DATA_WIDTH-1:0] PWDATA;
reg [ADDR_WIDTH-1:0] PADDR;
wire [DATA_WIDTH-1:0] PRDATA;


apb_sram apb_sram_A(
.PCLK(PCLK),
.PSEL(PSEL),
.PENABLE(PENABLE),
.PWRITE(PWRITE),
.PWDATA(PWDATA),
.PADDR(PADDR),
.PRESETn(PRESETn),
.CEN(CEN),
.PRDATA(PRDATA)
);

initial
    begin
    PRESETn<=0;
    PCLK<=0;
    PSEL<=0;
    #20;
    PRESETn<=1;
    PSEL<=1;
    PWRITE<=1;
    PADDR<=32'h0;
    PWDATA<=16'b1000_0000_0000_0000;
    #20;
    PADDR<=32'h1;
    PWDATA<=16'b1000_0000_0000_0001; 
    #20;
    PADDR<=32'h2;
    PWDATA<=16'b0000_0000_0000_0011;
    #20;
    PADDR<=32'h3;
    PWDATA<=16'b1111_1111_1111_1111;
    #20;
    PWRITE<=0;
    PADDR<=32'h0;   
    #20;
    PWRITE<=0;
    PADDR<=32'h2;         
    end

always #5 PCLK=~PCLK;

endmodule

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