HDLbits答案更新系列5(3 Circuits 3.1 Combinational logic 3.1.1 Basic Gates 3.1.2 Multiplexers)

目录

前言

3.1 Combinational logic

3.1.1 Basic Gates

3.1.1.1 Wire(Exams/m2014 q4h)

3.1.1.2 GND(Exams/m2014 q4i)

3.1.1.3 NOR(Exams/m2014 q4e)

3.1.1.4 Another gate(Exams/m2014 q4f)

3.1.1.5 Two gates(Exams/m2014 q4g)

3.1.1.6 More logic gates(Gates)

3.1.1.7 7420 chip(7420)

3.1.1.8 Truth tables(Truthtable1)

3.1.1.9 Two-bit equality(Mt2015 eq2)

3.1.1.10 Simple circuit A(Mt2015 q4a)

3.1.1.11 Simple circuit B(Mt2015 q4b)

3.1.1.12 Combine circuit A and B(Mt2015 q4)

3.1.1.13 Ring or vibrate?(Ringer)

3.1.1.14 Thermostat(Thermostat)

3.1.1.15 3-bit population count(Popcount3)

3.1.1.16 Gates and vectors(Gatesv)

3.1.1.17 Even longer vectors(Gatesv100)

3.1.2 Multiplexers

3.1.2.1 2-to-1 multiplexer(Mux2to1)

3.1.2.2 2-to-1 bus multiplexer(Mux2to1v)

3.1.2.3 9-to-1 multiplexer(Mux9to1v)

3.1.2.4 256-to-1 multiplexer(Mux256to1)

3.1.2.5 256-to-1 4bit multiplexer(Mux256to1v)

结语

HDLbits网站链接


前言

今天更新两个小节内容,这些内容都是比较基础的内容。

3.1 Combinational logic

3.1.1 Basic Gates

3.1.1.1 Wire(Exams/m2014 q4h)

module top_module (
    input in,
    output out);
    
    assign out = in;

endmodule

3.1.1.2 GND(Exams/m2014 q4i)

module top_module (
    output out);
    
    assign out = 1'b0;

endmodule

3.1.1.3 NOR(Exams/m2014 q4e)

module top_module (
    input in1,
    input in2,
    output out);

    assign out = ~(in1 | in2);
    
endmodule

3.1.1.4 Another gate(Exams/m2014 q4f)

module top_module (
    input in1,
    input in2,
    output out);
    
    assign out = in1 & ~in2;

endmodule

3.1.1.5 Two gates(Exams/m2014 q4g)

module top_module (
    input in1,
    input in2,
    input in3,
    output out);
    
    assign out = (in1 ~^ in2) ^ in3;

endmodule

3.1.1.6 More logic gates(Gates)

module top_module( 
    input a, b,
    output out_and,
    output out_or,
    output out_xor,
    output out_nand,
    output out_nor,
    output out_xnor,
    output out_anotb
);
    
    assign out_and = a & b;
    assign out_or = a | b;
    assign out_xor = a ^ b;
    assign out_nand = ~(a & b);
    assign out_nor = ~(a | b);
    assign out_xnor = a ~^ b;
    assign out_anotb = a & ~b;

endmodule

3.1.1.7 7420 chip(7420)

module top_module ( 
    input p1a, p1b, p1c, p1d,
    output p1y,
    input p2a, p2b, p2c, p2d,
    output p2y );
    
    assign p1y = ~(p1a & p1b & p1c & p1d);
    assign p2y = ~(p2a & p2b & p2c & p2d);

endmodule

3.1.1.8 Truth tables(Truthtable1)

module top_module( 
    input x3,
    input x2,
    input x1,  // three inputs
    output f   // one output
);
    assign f = x3 & x1 | x2 & x1 | ~x3 & x2;

endmodule

3.1.1.9 Two-bit equality(Mt2015 eq2)

module top_module ( input [1:0] A, input [1:0] B, output z ); 
    
    assign z = (A == B) ? 1'b1 : 1'b0;

endmodule

3.1.1.10 Simple circuit A(Mt2015 q4a)

module top_module (input x, input y, output z);
    
    assign z = (x ^ y) & x;

endmodule

3.1.1.11 Simple circuit B(Mt2015 q4b)

module top_module ( input x, input y, output z );
    
    assign z = x ~^ y;

endmodule

3.1.1.12 Combine circuit A and B(Mt2015 q4)

module top_module (input x, input y, output z);
    
    wire za;
    wire zb;
    
    assign za = (x ^ y) & x;
    assign zb = x ~^ y;
    assign z = (za | zb) ^ (za & zb);

endmodule

3.1.1.13 Ring or vibrate?(Ringer)

module top_module (
    input ring,
    input vibrate_mode,
    output ringer,       // Make sound
    output motor         // Vibrate
);
    
    assign ringer = ~vibrate_mode & ring;
    assign motor = vibrate_mode & ring;

endmodule

3.1.1.14 Thermostat(Thermostat)

module top_module (
    input too_cold,
    input too_hot,
    input mode,
    input fan_on,
    output heater,
    output aircon,
    output fan
); 

    assign heater = too_cold & mode;
    assign aircon = too_hot & ~mode;
    assign fan = fan_on | heater | aircon;

endmodule

3.1.1.15 3-bit population count(Popcount3)

module top_module( 
    input [2:0] in,
    output [1:0] out );
    
    reg [1:0] out_temp;
    integer i;
    
    always@(*)begin
        out_temp = 2'd0;
        for(i = 0; i <= 2; i = i + 1)begin
            out_temp = out_temp + in[i];
        end
    end
    
    assign out = out_temp;

endmodule

这种方式会产生锁存器,不建议这样做,博主为了省事儿,建议用查找表

3.1.1.16 Gates and vectors(Gatesv)

module top_module( 
    input [3:0] in,
    output [2:0] out_both,
    output [3:1] out_any,
    output [3:0] out_different );
    
    assign out_both = in[3:1] & in[2:0];
    assign out_any = in[3:1] | in[2:0];
    assign out_different = {in[0], in[3:1]} ^ in;
    
    /*
    //second way
    assign out_both[0] = in[1] & in[0];
    assign out_both[1] = in[2] & in[1];
    assign out_both[2] = in[3] & in[2];
    assign out_any[1] = in[1] | in[0];
    assign out_any[2] = in[2] | in[1];
    assign out_any[3] = in[3] | in[2];
    assign out_different[0] = in[1] ^ in[0];
    assign out_different[1] = in[2] ^ in[1];
    assign out_different[2] = in[3] ^ in[2];
    assign out_different[3] = in[0] ^ in[3];
    */
        
endmodule

第二种方法工作量大,不建议用,当然在不熟悉语法的情况下,可以用第二种。

3.1.1.17 Even longer vectors(Gatesv100)

module top_module( 
    input [99:0] in,
    output [98:0] out_both,
    output [99:1] out_any,
    output [99:0] out_different );
    
    assign out_both = in[99:1] & in[98:0];
    assign out_any = in[99:1] | in[98:0];
    assign out_different = {in[0], in[99:1]} ^ in;

endmodule

3.1.2 Multiplexers

3.1.2.1 2-to-1 multiplexer(Mux2to1)

module top_module( 
    input a, b, sel,
    output out ); 
    
    assign out = sel ? b : a;
    
    //second way
    //assign out = (sel & b) | (~sel & a);

endmodule

第二种方法是门级描述,为了清楚选择器内部结构,平时用的不多。

3.1.2.2 2-to-1 bus multiplexer(Mux2to1v)

module top_module( 
    input [99:0] a, b,
    input sel,
    output [99:0] out );
    
    assign out = sel ? b : a;

endmodule

3.1.2.3 9-to-1 multiplexer(Mux9to1v)

module top_module( 
    input [15:0] a, b, c, d, e, f, g, h, i,
    input [3:0] sel,
    output reg [15:0] out );
    
    always@(*)begin
        case(sel)
            4'd0:begin
                out = a;
            end
            4'd1:begin
                out = b;
            end
            4'd2:begin
                out = c;
            end
            4'd3:begin
                out = d;
            end
            4'd4:begin
                out = e;
            end
            4'd5:begin
                out = f;
            end
            4'd6:begin
                out = g;
            end
            4'd7:begin
                out = h;
            end
            4'd8:begin
                out = i;
            end
            default:begin
                out = 16'hffff;
            end
        endcase
    end

endmodule

3.1.2.4 256-to-1 multiplexer(Mux256to1)

module top_module( 
    input [255:0] in,
    input [7:0] sel,
    output reg out );
   
    assign out = in[sel];

endmodule

这种方式真是巧妙,不用大家用case一个一个列了,强烈建议大家使用这种方法!

3.1.2.5 256-to-1 4bit multiplexer(Mux256to1v)

module top_module( 
    input [1023:0] in,
    input [7:0] sel,
    output [3:0] out );
    
    assign out = in[sel * 4 +: 4];
    
    //second way
    //assign out = {in[sel * 4 + 3], in[sel * 4 + 2], in[sel * 4 + 1], in[sel * 4]};

endmodule

这种写法是verilog 2001标准中新增加的,是向量部分选择的意思,如果sel等于0,in[sel * 4 +: 4]代表从0开始向上数4位,即in[3:0],建议大家学习使用这种方法,在sel位宽较大是可以有效减小工作量。

结语

今天更新两个小节,这两个小节内容比较基础,但又是必须要掌握的,希望大家能够去练习一下,毕竟每个success也会给自己带来一点小小的成就感。最后,欢迎大家指出我的错误,我会尽快核对~

HDLbits网站链接

https://hdlbits.01xz.net/wiki/Main_Page

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