基于FPGA的数字电子密码锁Verilog开发Modelsim仿真

部分参考代码

(末尾附文件)

module MiMaSuo (
	input clk,
	input rst_n,
	
	input ling,
	input yi,
	input er,
	input san,
	input si,
	input wu,
	input liu,
	input qi,
	input ba,
	input jiu,
	
	input gm,
	input del,
	input unlock,
	
	output wrongled,
	output lockled,
	output openled,
	output [7:0] seg0,
	output [7:0] seg1,
	output [7:0] seg2,
	output [7:0] seg3,
	output [7:0] seg4,
	output [7:0] seg5
);
	
wire [23:0] data8_r;      //显示在数码管上的值

wire[3:0] data0;
wire[3:0] data1;
wire[3:0] data2;
wire[3:0] data3;
wire[3:0] data4;
wire[3:0] data5;

wire gm_r;
wire del_r;

wire ling_r;
wire yi_r;
wire er_r;
wire san_r;
wire si_r;
wire wu_r;
wire liu_r;
wire qi_r;
wire ba_r;
wire jiu_r;
wire unlock_r;
	
	key k0 (.clk(clk), .rst_n(rst_n), .key_n(ling),	.key_out(ling_r));
	key k1 (.clk(clk), .rst_n(rst_n), .key_n(yi),	.key_out(yi_r));
	key k2 (.clk(clk), .rst_n(rst_n), .key_n(er),	.key_out(er_r));
	key k3 (.clk(clk), .rst_n(rst_n), .key_n(san),	.key_out(san_r));
	key k4 (.clk(clk), .rst_n(rst_n), .key_n(si),	.key_out(si_r));
	key k5 (.clk(clk), .rst_n(rst_n), .key_n(wu),	.key_out(wu_r));
	key k6 (.clk(clk), .rst_n(rst_n), .key_n(liu),	.key_out(liu_r));
	key k7 (.clk(clk), .rst_n(rst_n), .key_n(qi),	.key_out(qi_r));
	key k8 (.clk(clk), .rst_n(rst_n), .key_n(ba),	.key_out(ba_r));
	key k9 (.clk(clk), .rst_n(rst_n), .key_n(jiu),	.key_out(jiu_r));

	key k10 (.clk(clk), .rst_n(rst_n), .key_n(gm),	.key_out(gm_r));
	key k11 (.clk(clk), .rst_n(rst_n), .key_n(del),	.key_out(del_r));
	key k12 (.clk(clk), .rst_n(rst_n), .key_n(unlock),	.key_out(unlock_r));

	 //-----------------------输入值控制模块------------------------
	dingceng p1 (.clk(clk), .rst_n(rst_n), .ling(~ling_r), .yi(~yi_r), .er(~er_r), .san(~san_r), .si(~si_r), 
	.wu(~wu_r), .liu(~liu_r), .qi(~qi_r), .ba(~ba_r), .jiu(~jiu_r), .gm(~gm_r), .del(~del_r), .unlock(~unlock_r), .data8(data8_r), .wrongled(wrongled), .lockled(lockled), .openled(openled));
	 //-----------------------动态显示控制模块------------------------ 
	show pp1 (.clk(clk), .rst_n(rst_n), .data8(data8_r), .data0(data0), .data1(data1), .data2(data2), .data3(data3),.data4(data4), .data5(data5));
	 //-----------------------数码管显示模块------------------------
	seg7 s1 (.clk(clk),.rst_n(rst_n), .data0(data0), .data1(data1), .data2(data2), .data3(data3), .data4(data4), .data5(data5),.seg0(seg0), .seg1(seg1), .seg2(seg2), .seg3(seg3), .seg4(seg4), .seg5(seg5));
 
endmodule
 

.

链接：https://pan.baidu.com/s/1fWTeeahswxwVfWLEwi9TNg
提取码：d334

.