关于FPGA的琐事_0x00 八路彩灯控制程序

EDA这个课只听了两节，今天考前复习，看复习题上的程序写的是十分秀气，就记录了下来。
代码：

module caideng(clk,ledout,reset);
input reset,clk;                       //定义输入：复位，时钟脉冲
output [7:0] ledout;                //定义8位led输出
integer i;                                 //源代码中定义但未调用
reg [7:0] ledout;                     //定义8为led输出为寄存器（reg）型
reg [2:0] count;                      //定义计数count
reg [4:0] count2;                    //定义计数count2
reg clkflag;                             //定义状态标志
reg [1:0] in;                            //标志
always@(posedge clk)       //敏感脉冲表达式 设置为clk时钟信号上升沿触发
begin 
  if(!reset)
    count=0;
  else if(count<=3)
    begin
      clkflag<=0;
      count<=count+1;
    end
  else if(count<7)
    begin 
       clkflag<=1;
        count<=count+1;
     end
    else if(count==7)
      begin 
        clkflag<=1;
         count=0;
          end
  else 
  begin
    clkflag<=1;
    count=count+1;
  end
end
always@(posedge clk)
  begin
    if(!reset)
      count2<=0;
    else if(count2<7)
      begin 
        in<=2'b00;
        count2=count2+1;
      end
    else if(count2<=15)
      begin 
        in<=2'b01;
        count2=count2+1;
       end
      else if(count2<23)
        begin 
          in<=2'b10;
           count2<=count2+1;
         end
        else if(count2==23)
           begin 
             in<=2'b10;
             count2<=0;
            end
    else 
     begin
       in=2'bZZ;
    count2<=0;
  end
end
always@(posedge count or reset)
  if(!reset)
    ledout<=8'h00;
  else 
begin
 case(in)
  2'b00: if(clkflag)
    ledout=8'hFF;
              else
    ledout=8'h00;
  2'b01:
  case(count)
  'h0:ledout=8'h80;
  'h0:ledout=8'h40;
  'h2:ledout=8'h20;
  'h3:ledout=8'h10;
  'h4:ledout=8'h08;
  'h5:ledout=8'h04;
  'h6:ledout=8'h02;
  'h7:ledout=8'h01;
defualt:ledout=8'h00;
endcase
2'b10: if(clkflag)
  ledout=8'hAA;
  else ledout=8'h55;
  defualt;:
  ledout=8'h00;
end case 
end
endmodule