MATLAB HDL Coder从无到有

MATLAB HDL

Name

MATLAB HDL

Description

This repository documents how to use MATLAB’s Simulink’s HDL tools to accelerate HDL-related work.

Installation

module load matlab/R2022a

Steps

First go through initial steps. Then look around advanced steps.
name in grey basically means click a button with a greyed name.

Inital steps

1. Create a directory as your work space, such as “hdl_coder”.

2. Run commands: cd and matlab.

3. Click Simulink

4. Create a Blank Model if starting from scratch. Else choose others.

5. Save this model with a desired file name.

6. Add blocks. Click Library Browser or double-click blank area in the canvas.

7. Select functional blocks from “HDL Coder”

8. Add functional blocks by right-click -> Add block to model .

9. Add input and output ports via “Ports & Subsystems” or “Sinks” or “Sources” class.

10. Connect IOs of each block by wire.

11. Click App -> HDL Coder

12. Now specify configurations

    1. Click Settings -> HDL Code Generation Settings
    2. In “HDL Code Generation”, set “Language” as “Verilog”, set “Folder” as “/hdlsrc”.
    3. Hardware Implementation -> set “Device Vendor” as “ASIC/FPGA”. (If doing ASIC/FPGA Implementation)
    4. Global Settings -> Clock settings -> Reset type -> Choose “Synchronous”.
    5. Apply and OK.

13. In the “HDL CODE” tab, click Generate HDL Code.

14. If there is an error:

    For the block ‘xxx’
    Signals of type ‘Double’ will not generate synthesizable HDL. For synthesizable HDL code, set the “Library” option to “Native Floating Point”. For non-synthesizable and simulation-only HDL code, set the “Check for presence of reals in generated HDL code” diagnostic to “Warning” or “None”.

    Double-click all inports one by one -> Signal Attributes -> change “Data type” to something other than “double”.

15. Generate HDL Code. Get .v

Simulation

1. Click wires of interest, hover mouse to “Log Selected Singal”, click.

2. Select desired sources.

3. In “SIMULATION” tab -> “SIMULATE” area, click Run.

4. If there is an error related to variable-step or fixed-step, change Settings -> “Solver” -> “Solver selection” -> “Type” to “Fixed-step”

5. In “SIMULATION” tab -> “REVIEW RESULTS” area, click Data Inspector or Logic Analyzer.

Advanced steps

1. Change inports’ Singal Attributes -> “Port Dimension” to do vector operation.
2. Add blocks of “subsystem” to achieve hierarchy. This is also useful when wanting one specific component’s Verilog code.
3. Simulation’s stimulation data import. Settings -> “Data Import/Export” -> “Input” -> type the structure or time series
4. Automation commands:

open_system("xxx")
out=sim("xxx")
logsout=out.logsout
logsout.get(<n>).Values.<values of interest>

Contributing

Help me with automating all aforementioned processes, meaning, find equivalent MATLAB commands for them.

Project status

Ongoing

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Errors & solutions:

Here documented common errors and their solutions.

1. Error:

   For the block ‘xxx/Divider’ Product block with divide input (/) only supports Saturation “On”.

   Solution: In Signal Attributes -> tick “Sarutate on integer overflow” and choose “Integer rounding mode” to be “Simplest” or “Zero”.

2. Cannot generate code for Sqrt:

   Solution: change Sqrt’s output type as fixed points. No need to change the floating point library in configuration. Keep “None”.

3. Cannot generate code for Exp:
   Solution: add a data type converter to convert FX to FP.

4. Simulation’s stimulations do not match workspace’s time and value:
   Solution: Settings -> “Solver” -> “Solver selection” -> “Type” := “Fixed-step” , “Solver” := “discrete (no continuous states)” & “Solver details” -> “Fixed-step size” := unit time frame that you set in the workspace or timetable