HDLbits---Circuits---Sequential Logic---Latches and Flip-Flops

1.dff

module top_module (
    input clk,    // Clocks are used in sequential circuits
    input d,
    output reg q );//

    // Use a clocked always block
    //   copy d to q at every positive edge of clk
    //   Clocked always blocks should use non-blocking assignments
    always@(posedge clk) begin
        q=d;
    end
endmodule

2.DFF8

module top_module (
    input clk,
    input [7:0] d,
    output [7:0] q
);
    always@(posedge clk) begin
        q<=d;
    end
endmodule

3.dff8r

module top_module (
    input clk,
    input reset,            // Synchronous reset
    input [7:0] d,
    output [7:0] q
);
    always@(posedge clk) begin
        if(reset) begin
            q=0; end
        else
            q=d;
    end
endmodule

4.dff8p

module top_module (
    input clk,
    input reset,
    input [7:0] d,
    output [7:0] q
);
    always@(negedge clk) begin
        if(reset) begin
            q=8'h34; end
        else
            q=d;
    end
          
endmodule

5.Dff8ar

module top_module (
    input clk,
    input areset,   // active high asynchronous reset
    input [7:0] d,
    output [7:0] q
);
    always@(posedge clk or posedge areset ) begin
        if(areset) begin
            q<=0; end
        else begin
            q<=d; end
    end
            
endmodule

6.DFF16e

module top_module (
    input clk,
    input resetn,
    input [1:0] byteena,
    input [15:0] d,
    output [15:0] q
);
    always@(posedge clk) begin
        if(resetn==0)
            q<=0; 
    else
        begin 
            if(byteena==2'b10)
                q[15:8]<=d[15:8]; 
            else
                if(byteena==2'b01)
                    q[7:0]<=d[7:0]; 
            else 
                if(byteena==2'b11)
                    q<=d;
        end
    end
endmodule

7.Exams/m2014 q4a

module top_module (
    input d, 
    input ena,
    output q);

always @(*) begin
    if (ena) begin
        q = d;
    end
end
 

endmodule

8.exams/m2014_q4b

module top_module (
    input clk,
    input d, 
    input ar,   // asynchronous reset
    output q);

always @(posedge clk or posedge ar) begin
    if (ar) begin
        q <= 'd0;
    end
    else begin
        q <= d;
    end
end
endmodule

9.exams/m2014_q4c

module top_module (
    input   clk,
    input   d, 
    input   r,   
    output  q
);
always @(posedge clk) begin
    if (r) begin
        q <= 'd0;
    end
    else begin
        q <= d;
    end
end
 
endmodule

10.exams/m2014_q4d

module top_module (
    input clk,
    input in, 
    output out);
  
    always@(posedge clk) begin
       out<=in^out;
    end
endmodule

11.mt2015_muxdff

module top_module (
    input clk,
    input L,
    input r_in,
    input q_in,
    output reg Q);

    always@(posedge clk) begin
        if(L==1)
            Q<=r_in; 
        else
            if(L==0)
                Q<=q_in; 
    end
endmodule

12.Exams/2014 q4a

module top_module (
    input clk,
    input w, R, E, L,
    output Q
);
wire p;
    assign p=E?w:Q;
    always@(posedge clk) begin
        if(L==1)
            Q<=R;
        else if(L==0)
            Q<=p;
    end
endmodule

13.exams/ece241_2014_q4

module top_module (
    input clk,
    input x,
    output z
); 
wire q0,q1,q2;
    always@(posedge clk) begin
        q2<=x^q2;
        q1<=x&~q1;
        q0<=x|~q0;
    end
    assign z=~(q0|q1|q2); 
endmodule

14.exams/ece241_2013_q7

module top_module (
    input clk,
    input j,
    input k,
    output Q); 
    wire[1:0] t;
    assign t={j,k};
    always@(posedge clk) begin
        case(t)
            2'b00:Q<=Q;
            2'b01:Q<=0;
            2'b10:Q<=1;
            2'b11:Q<=~Q;
        endcase
    end
endmodule

15.Edgedetect

module top_module (
    input         clk,
    input  [7:0]  in,
    output [7:0]  pedge
);
reg [7:0]  in_reg;
always @(posedge clk) begin
    in_reg <= in;
end
always @(posedge clk) begin
    pedge <= in & (~in_reg);
end
endmodule

16.edgedetect2

module top_module (
    input         clk,
    input  [7:0]  in,
    output [7:0]  anyedge
);
reg [7:0]  in_reg;
always @(posedge clk) begin
    in_reg <= in;
end
always @(posedge clk) begin
    anyedge <= in ^ in_reg;
end
endmodule

17.edgecapture

module top_module (
    input          clk,
    input          reset,
    input  [31:0]  in,
    output [31:0]  out
);
reg [31:0]  in_reg;
 
always @(posedge clk) begin
    in_reg <= in;
end
 
always @(posedge clk) begin
    if (reset) begin
        out <= 'd0;
    end
    else begin
        out <= ~in & in_reg | out;
    end
end
endmodule

18.dualedge

module top_module (
    input   clk,
    input   d,
    output  q
);
reg   d1,d2;
always @(posedge clk) begin
    d1 <= d;
end
always @(negedge clk) begin
    d2 <= d;
end
assign q = clk?d1:d2;
 
endmodule