1.Fsm1
module top_module(
input clk,
input areset, // Asynchronous reset to state B
input in,
output out);//
parameter A=0, B=1;
reg state, next_state;
always@(posedge clk or posedge areset) begin
if(areset)
state<=B;
else
state<=next_state;
end
always@(*) begin
case(state)
A: begin
if(in==1)
next_state<=A;
else
next_state<=B;
end
B: begin
if(in == 1'b1)
next_state = B;
else
next_state = A;
end
endcase
end
always@(*) begin
if(state==B)
out<=1;
else
out<=0;
end
endmodule
2.Fsm1s
module top_module(
input clk,
input reset, // Asynchronous reset to state B
input in,
output out);//
parameter A=0, B=1;
reg state, next_state;
always@(posedge clk ) begin
if(reset)
state<=B;
else
state<=next_state;
end
always@(*) begin
case(state)
A: begin
if(in==1)
next_state<=A;
else
next_state<=B;
end
B: begin
if(in == 1'b1)
next_state = B;
else
next_state = A;
end
endcase
end
always@(*) begin
if(state==B)
out<=1;
else
out<=0;
end
endmodule
3.Fsm2
module top_module(
input clk,
input areset, // Asynchronous reset to OFF
input j,
input k,
output out); //
parameter OFF=0, ON=1;
reg state, next_state;
always@(posedge clk or posedge areset) begin
if(areset)
state<=OFF;
else
state<=next_state;
end
always@(*) begin
case(state)
OFF:begin
if(j==0)
next_state<=OFF;
else
next_state<=ON;
end
ON: begin
if(k==0)
next_state<=ON;
else
next_state<=OFF;
end
endcase
end
always@(*) begin
if(state==OFF)
out<=0;
else
out<=1;
end
endmodule
4.Fsm2s
module top_module(
input clk,
input reset, // Asynchronous reset to OFF
input j,
input k,
output out); //
parameter OFF=0, ON=1;
reg state, next_state;
always@(posedge clk ) begin
if(reset)
state<=OFF;
else
state<=next_state;
end
always@(*) begin
case(state)
OFF:begin
if(j==0)
next_state<=OFF;
else
next_state<=ON;
end
ON: begin
if(k==0)
next_state<=ON;
else
next_state<=OFF;
end
endcase
end
always@(*) begin
if(state==OFF)
out<=0;
else
out<=1;
end
endmodule
5.Fsm3comb
module top_module(
input in,
input [1:0] state,
output [1:0] next_state,
output out); //
parameter A=0, B=1, C=2, D=3;
always@(*) begin
case(state)
A: begin
if(in==0)
next_state<=A;
else
next_state<=B; end
B: begin
if(in==0)
next_state<=C;
else
next_state<=B; end
C: begin
if(in==0)
next_state<=A;
else
next_state<=D; end
D: begin
if(in==0)
next_state<=C;
else
next_state<=B; end
endcase
end
assign out=(state==D);
endmodule
6.Fsm3onehot
module top_module(
input in,
input [3:0] state,
output [3:0] next_state,
output out); //
parameter A=0, B=1, C=2, D=3;
assign next_state[A] = (state[A] && ~in) | (state[C] && ~in);
assign next_state[B] = (state[B] && in) | (state[D] && in) | (state[A] && in);
assign next_state[C] = (state[B] && ~in) | (state[D] && ~in);
assign next_state[D] = (state[C] && in);
assign out = (state[D]);
endmodule
7.Fsm3
module top_module(
input clk,
input in,
input areset,
output out
);
//状态申明
parameter A = 4'b0001;
parameter B = 4'b0010;
parameter C = 4'b0100;
parameter D = 4'b1000;
parameter ON = 1;
parameter OFF = 0;
reg [3:0] state;
reg [3:0] next_state;
always @(posedge clk or posedge areset) begin
if (areset) begin
state <= A;
end
else begin
state <= next_state;
end
end
always @(*) begin
next_state = state;
case(state)
A:
case(in)
ON: next_state = B;
OFF: next_state = A;
endcase
B:
case(in)
ON: next_state = B;
OFF: next_state = C;
endcase
C:
case(in)
ON: next_state = D;
OFF: next_state = A;
endcase
D:
case(in)
ON: next_state = B;
OFF: next_state = C;
endcase
endcase
end
assign out = (state==D);
endmodule
8.Fsm3s
module top_module(
input clk,
input in,
input reset,
output out
);
parameter A = 4'b0001;
parameter B = 4'b0010;
parameter C = 4'b0100;
parameter D = 4'b1000;
parameter ON = 1;
parameter OFF = 0;
reg [3:0] state;
reg [3:0] next_state;
always @(posedge clk ) begin
if (reset) begin
state <= A;
end
else begin
state <= next_state;
end
end
always @(*) begin
next_state = state;
case(state)
A:
case(in)
ON: next_state = B;
OFF: next_state = A;
endcase
B:
case(in)
ON: next_state = B;
OFF: next_state = C;
endcase
C:
case(in)
ON: next_state = D;
OFF: next_state = A;
endcase
D:
case(in)
ON: next_state = B;
OFF: next_state = C;
endcase
endcase
end
assign out = (state==D);
endmodule
9.Exams/ece241 2013 q4
module top_module (
input clk,
input reset,
input [3:1] s,
output fr3,
output fr2,
output fr1,
output dfr
);
parameter A=0,B=1,C=2,D=3,E=4,F=5;
reg [2:0] state,next_state;
always @(*)
begin
case(state)
A:next_state = s[1]?B:A;
B:next_state = s[2]?D:(s[1]?B:A);
C:next_state = s[2]?D:(s[1]?C:A);
D:next_state = s[3]?F:(s[2]?D:C);
E:next_state = s[3]?F:(s[2]?E:C);
F:next_state = s[3]?F:E;
default:next_state = 'x;
endcase
end
always @(posedge clk)
begin
if(reset)
state <= A;
else
state <= next_state;
end
always @(*)
begin
case(state)
A:{fr3,fr2,fr1,dfr} = 4'b1111;
B:{fr3,fr2,fr1,dfr} = 4'b0110;
C:{fr3,fr2,fr1,dfr} = 4'b0111;
D:{fr3,fr2,fr1,dfr} = 4'b0010;
E:{fr3,fr2,fr1,dfr} = 4'b0011;
F:{fr3,fr2,fr1,dfr} = 4'b0000;
default: {fr3,fr2,fr1,dfr} = 'x;
endcase
end
endmodule
