Exams/ece241 2013 q4

 蓄水池问题

S3 S2 S1 

例如：000  代表 无水 ，需要使FR3, FR2, FR1 都打开（111）

S3 S2 S1     FR3 FR2 FR1

000                  111

001                011

011               001

111               000

fr代表水变深为0 ，水变少为1

module top_module (
    input clk,
    input reset,
    input [3:1] s,
    output fr3,
    output fr2,
    output fr1,
    output dfr
); 
    parameter B_S1 = 3'b000,  
    		B_S1_S2 = 3'b001,
    		B_S2_S3 = 3'b011,
    		A_S3 = 3'b111;
    
    reg [2:0] state;
    reg [2:0] next_state;
    
    always@ (posedge clk) begin
       state <= next_state;   //next_state 变化较快
    end 
    
    always@ (*)
        if(reset)
    		next_state <= B_S1;
    	else 
        	case({s[3], s[2], s[1]})
                B_S1: 
                        if(s[1]+s[2]+s[3] == 0)   
                    	    next_state <= B_S1;
                	    else  
                            next_state <= B_S1_S2;
                B_S1_S2: 
                        if(s[1]&& s[2] && ~s[3] )  
                    		next_state <= B_S2_S3;
               			 else if(s[1]+s[2]+s[3] == 0)
                    		next_state <= B_S1;
                    	else
                        	next_state <= B_S1_S2;
                B_S2_S3:
                         if(s[1] & s[2] && s[3]) 
                    		next_state <= A_S3;
                          else if(s[1] && ~s[2] && ~s[3])   
                    		next_state <= B_S1_S2;
                    	  else
                        	next_state <= B_S2_S3;
                A_S3:     
                        if(&s) 
                    	    next_state <= A_S3;
                	    else  
                            next_state <= B_S2_S3;
                default: next_state <= B_S1;
            endcase
    
	always@ (posedge clk)
        if(reset) begin
            {fr3, fr2, fr1} <= 3'b111;
        end
    else case ({s[3], s[2], s[1]})
        B_S1: {fr3, fr2, fr1} <= 3'b111;
        B_S1_S2: {fr3, fr2, fr1} <= 3'b011;
        B_S2_S3: {fr3, fr2, fr1} <= 3'b001;
        A_S3: {fr3, fr2, fr1} <= 3'b000;
        default:{fr3, fr2, fr1} <= 3'b111;
    endcase
    
    always@ (posedge clk)
        if(reset)  
            dfr <= 1;
    else if(state < next_state)  //水变深
            dfr <= 0;
    else if(state > next_state)   
            dfr <= 1;
    else 
        dfr <= dfr;
            
            
endmodule