[HDLBits] Count clock

Create a set of counters suitable for use as a 12-hour clock (with am/pm indicator). Your counters are clocked by a fast-running clk, with a pulse on ena whenever your clock should increment (i.e., once per second).

reset resets the clock to 12:00 AM. pm is 0 for AM and 1 for PM. hh, mm, and ss are two BCD (Binary-Coded Decimal) digits each for hours (01-12), minutes (00-59), and seconds (00-59). Reset has higher priority than enable, and can occur even when not enabled.

The following timing diagram shows the rollover behaviour from 11:59:59 AM to 12:00:00 PM and the synchronous reset and enable behaviour.

module top_module(
    input clk,
    input reset,
    input ena,
    output pm,
    output [7:0] hh,
    output [7:0] mm,
    output [7:0] ss); 
    wire [2:0] ena_wire;  //进位标识符
    reg pm_test;
    assign ena_wire[0]=ena;
    bcd seconds(clk,reset,ena_wire[0],ss);   //sec
    assign ena_wire[1]=(ss==8'h59)&&ena;
    bcd minutes(clk,reset,ena_wire[1],mm);   //min
    assign ena_wire[2]=(ss==8'h59&&mm==8'h59)&&ena;
    bcd_hour hours(clk,reset,ena_wire[2],hh); //hour
    always@(posedge clk) begin                 //p.m.
        if(reset)
            pm_test<=0;
        else if(ss==8'h59&&mm==8'h59&&hh==8'h11)
            pm_test=~pm_test;
        else;
    end
    assign pm=pm_test;
endmodule

module bcd(
    input clk,
	input reset,
	input ena,
    output reg[7:0] q
);
    always@(posedge clk) begin
        if(reset)
            q<=0;
        else if(ena) begin    //若需进位
            if(q==8'h59)      //且到了59，进位为0
                q<=0;
            else if(q[3:0]==9) begin   //不是59就要考虑有两位数字，个位若为9则进位，十位+1
                q[3:0]<=4'b0;
                q[7:4]<=q[7:4]+1;
            end
            else                        //个位不为9就不进位，个位+1
                q[3:0]<=q[3:0]+1;
        end
        //else;
    end
endmodule

module bcd_hour(
    input clk,
	input reset,
	input ena,
    output reg[7:0] q
    //output pm
);
    always@(posedge clk) begin
        //pm=0;
        if(reset)
            q<=8'h12;          //和上面几乎一样，就这里reset是12需要注意
        else if(ena) begin
            if(q==8'h12) begin
                q<=1;
                //pm=~pm;
            end
            else if(q[3:0]==9) begin
                q[3:0]<=4'b0;
                q[7:4]<=q[7:4]+1;
            end
            else
                q[3:0]<=q[3:0]+1;
        end
        //else;
    end
endmodule

/*
这道题有坑，就是ss mm hh这种都有两位，ss这两位之间也需要进位。
以及这里的进位判定都是'h59，不知道为什么不是'd59
以及分钟和秒用的bcd计数器可以是同一个，但小时的要单独写。
HDLBits resoultion 的答案我没看懂


*/

这道题有坑，就是ss mm hh这种都有两位，ss这两位之间也需要进位。
以及这里的进位判定都是'h59，不知道为什么不是'd59
以及分钟和秒用的bcd计数器可以是同一个，但小时的要单独写。
HDLBits resoultion 的答案我没看懂