HDLbits答案
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- Counters
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- Shift Regesters
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- 4-bit shift register
- Left/right rotator
- Left/right arithmetic shift by 1 or 8
- 5-bit LFSR
- 3-bit LFSR
- 32-bit LFSR
- Shift register Exams/m2014 q4k
- Shift register Exams/2014 q4b
- 3-inpit LUT Exams/ece241 2013 q12
- more Circuits
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- Finite State Machines
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- PS/2 packet parser and datapath
- Serial receiver
- Serial receiver and datapath
Counters
12-hour clock
module top_module(
input clk,
input reset,
input ena,
output pm,
output [7:0] hh,
output [7:0] mm,
output [7:0] ss);
reg [3:0] ss_ones,mm_ones,hh_ones,ss_tens,mm_tens,hh_tens;
always @(posedge clk)
begin
if (reset) begin ss_ones<=0;end
else if (ena) begin if(ss_ones==4'd9) begin ss_ones<=0;end
else ss_ones<=ss_ones+1;
end
else ss_ones<=ss_ones;
end
always @(posedge clk)
begin
if (reset) begin ss_tens<=0;end
else if (ss_ones==4'd9&&ena)begin
if (ss_tens==4'd5)begin ss_tens<=0;end
else ss_tens<=ss_tens+1;
end
else ss_tens<=ss_tens;
end
always @(posedge clk)
begin
if (reset) begin mm_ones<=0; end
else if (ss_tens==4'd5&&ss_ones==4'd9&&ena) begin
if (mm_ones==4'd9)begin mm_ones<=0;end
else mm_ones<=mm_ones+1;
end
else mm_ones<=mm_ones;
end
always @(posedge clk)
begin
if (reset) begin mm_tens<=0; end
else if (mm_ones==4'd9&&ss_tens==4'd5&&ss_ones==4'd9&&ena) begin
if (mm_tens==4'd5) begin mm_tens<=0; end
else mm_tens<=mm_tens+1;
end
else mm_tens<=mm_tens;
end
always @(posedge clk)
begin
if (reset) begin hh_ones<=4'd2;end
else if (mm_tens==4'd5&&mm_ones==4'd9&&ss_tens==4'd5&&ss_ones==4'd9&&ena) begin
if (hh_ones==4'd9)begin hh_ones<=0;end
else if (hh_ones==2&&hh_tens==1)begin hh_ones<=1;end
else hh_ones<=hh_ones+1;
end
end
always @(posedge clk)
begin
if (reset) begin hh_tens<=4'd1;end
else if (mm_tens==4'd5&&mm_ones==4'd9&&ss_tens==4'd5&&ss_ones==4'd9&&ena)begin
if (hh_ones==2&&hh_tens==1)begin hh_tens<=0;end
else if (hh_ones==4'd9) begin hh_tens<=4'd1;end
end
end
always@(posedge clk)
begin
if (reset) begin pm<=0;end
else if (hh_ones==1&&hh_tens==1&&mm_tens==4'd5&&mm_ones==4'd9&&ss_tens==4'd5&&ss_ones==4'd9)begin
pm<=~pm;end
end
assign hh={hh_tens,hh_ones};
assign mm={mm_tens,mm_ones};
assign ss={ss_tens,ss_ones};
endmodule
Shift Regesters
4-bit shift register
module top_module(
input clk,
input areset, // async active-high reset to zero
input load,
input ena,
input [3:0] data,
output reg [3:0] q);
always @(posedge clk,posedge areset)
begin
if (areset) begin q<=4'd0;end
else if (load) begin q<=data;end
else if (ena) begin q<=q>>1; end
else q<=q;
end
endmodule
Left/right rotator
module top_module(
input clk,
input load,
input [1:0] ena,
input [99:0] data,
output reg [99:0] q);
always @(posedge clk)
begin
if (load) begin q<=data;end
else case(ena)
2'b01: begin q<={q[0],q[99:1]}; end
2'b10: begin q<={q[98:0],q[99]}; end
default : begin q<=q;end
endcase
end
endmodule
Left/right arithmetic shift by 1 or 8
module top_module(
input clk,
input load,
input ena,
input [1:0] amount,
input [63:0] data,
output reg [63:0] q);
always @(posedge clk )
begin
if (load) begin q<=data;end
else begin if (ena) begin
case (amount)
2'b00 : q<=q<<1;
2'b01 : q<=q<<8;
2'b10 : q<={q[63],q[63:1]};
2'b11 : q<={{8{q[63]}},q[63:8]};
endcase
end
else q<=q;
end
end
endmodule
5-bit LFSR
module top_module(
input clk,
input reset, // Active-high synchronous reset to 5'h1
output [4:0] q
);
reg [4:0] temp_q;
always @(posedge clk)
begin
if (reset) begin q<=5'h1;end
else begin
q[4]<=q[0];
q[3]<=q[4];
q[2]<=q[3]^q[0];
q[1]<=q[2];
q[0]<=q[1];
end
end
endmodule
3-bit LFSR
module top_module (
input [2:0] SW, // R
input [1:0] KEY, // L and clk
output [2:0] LEDR); // Q
always @(posedge KEY[0])
begin
if (KEY[1]) begin LEDR<=SW;end
else begin LEDR[0]<=LEDR[2];
LEDR[1]<=LEDR[0];
LEDR[2]<=LEDR[2]^LEDR[1];
end
end
endmodule
32-bit LFSR
module top_module(
input clk,
input reset, // Active-high synchronous reset to 32'h1
output [31:0] q
);
reg [31:0] q_next;
always @(posedge clk)
begin
if (reset) begin q<=32'b1;end
else q<=q_next;
end
always @(*)
begin
q_next={q[0], q[31:1]};
q_next[21]=q[22]^q[0];
q_next[1]=q[2]^q[0];
q_next[0]=q[1]^q[0];
end
endmodule
Shift register Exams/m2014 q4k
module top_module (
input clk,
input resetn, // synchronous reset
input in,
output out);
reg [3:0] Q;
always @(posedge clk)
begin
if (~resetn) begin Q<=4'b0;end
else begin Q<={in,Q[3:1]};end
end
assign out=Q[0];
endmodule
Shift register Exams/2014 q4b
module top_module (
input [3:0] SW,
input [3:0] KEY,
output [3:0] LEDR
); //
MUXDFF muxdff0(SW[3],KEY[3],KEY[0],KEY[1],KEY[2],LEDR[3]);
MUXDFF muxdff1(SW[2],LEDR[3],KEY[0],KEY[1],KEY[2],LEDR[2]);
MUXDFF muxdff2(SW[1],LEDR[2],KEY[0],KEY[1],KEY[2],LEDR[1]);
MUXDFF muxdff3(SW[0],LEDR[1],KEY[0],KEY[1],KEY[2],LEDR[0]);
endmodule
module MUXDFF (
input R,
input w,
input clk,
input E,
input L,
output Q);
wire temp ;
assign temp = L?R:(E?w:Q);
always @(posedge clk)
begin
Q<=temp;
end
endmodule
3-inpit LUT Exams/ece241 2013 q12
module top_module (
input clk,
input enable,
input S,
input A, B, C,
output Z );
reg [7:0] Q;
always @(posedge clk)
begin
if (~enable) begin Q<=Q;end
else begin Q<={Q[6:0],S};end
end
always @(*)
begin
case ({A,B,C})
3'b000 : Z = Q[0];
3'b001 : Z = Q[1];
3'b010 : Z = Q[2];
3'b011 : Z = Q[3];
3'b100 : Z = Q[4];
3'b101 : Z = Q[5];
3'b110 : Z = Q[6];
3'b111 : Z = Q[7];
endcase
end
endmodule
more Circuits
Rule90
module top_module(
input clk,
input load,
input [511:0] data,
output [511:0] q );
reg [511:0] left;
reg [511:0] right;
assign left=q<<1;
assign right=q>>1;
always @(posedge clk)
begin
if (load) begin q<=data;end
else q<=left^right;
end
endmodule
Rule110
module top_module(
input clk,
input load,
input [511:0] data,
output [511:0] q
);
reg [511:0] left;
reg [511:0] right;
assign left=q>>1;
assign right=q<<1;
always @(posedge clk)
begin
if (load) begin q<=data;end
else q<=right&~q|~left&right|~right&q;
end
endmodule
Finite State Machines
PS/2 packet parser and datapath
module top_module(
input clk,
input [7:0] in,
input reset, // Synchronous reset
output [23:0] out_bytes,
output done);
parameter s0=2'd0, s1=2'd1,s2=2'd2,s3=2'd3;
reg [1:0] state,next_state;
reg [23:0] temp;
always @(posedge clk)
begin
if (reset) state<=s0;
else state<=next_state;
end
always @(*)
begin
case (state)
s0 : next_state=in[3]?s1:s0;
s1 : next_state=s2;
s2 : next_state=s3;
s3 : next_state=in[3]?s1:s0;
default : next_state=s0;
endcase
end
always @(posedge clk)
begin
if (reset) temp=23'b0;
else temp={temp[15:0],in};
end
assign done=(state==s3);
assign out_bytes=done?temp:23'b0;
endmodule
Serial receiver
parameter s0=4'd0,s1=4'd1,s2=4'd2,s3=4'd3,s4=4'd4,s5=4'd5,s6=4'd6;
parameter s7=4'd7,s8=4'd8,s9=4'd9,s10=4'd10,s11=4'd11;
reg [3:0] state, next_state;
always @(*)
begin
case (state)
s0 : next_state=in?s0:s1; //没有识别到起始位
s1 : next_state=s2; //识别到起始位
s2 : next_state=s3; //1
s3 : next_state=s4;
s4 : next_state=s5;
s5 : next_state=s6;
s6 : next_state=s7;
s7 : next_state=s8;
s8 : next_state=s9;
s9 : next_state=in?s10:s11;
s10 : next_state=in?s0:s1; //识别到结束位，成功接收
s11 : next_state=in?s0:s11;
endcase
end
always @(posedge clk)
begin
if (reset) state<=s0;
else state<=next_state;
end
assign done=(state==s10);
Serial receiver and datapath
module top_module(
input clk,
input in,
input reset, // Synchronous reset
output [7:0] out_byte,
output done
); //
parameter s0=4'd0,s1=4'd1,s2=4'd2,s3=4'd3,s4=4'd4,s5=4'd5,s6=4'd6;
parameter s7=4'd7,s8=4'd8,s9=4'd9,s10=4'd10,s11=4'd11;
reg [3:0] state, next_state;
reg [8:0] temp;
always @(*)
begin
case (state)
s0 : next_state=in?s0:s1; //没有识别到起始位
s1 : next_state=s2; //识别到起始位
s2 : next_state=s3; //1
s3 : next_state=s4;
s4 : next_state=s5;
s5 : next_state=s6;
s6 : next_state=s7;
s7 : next_state=s8;
s8 : next_state=s9;
s9 : next_state=in?s10:s11;
s10 : next_state=in?s0:s1; //识别到结束位，成功接收
s11 : next_state=in?s0:s11;
endcase
end
always @(posedge clk)
begin
if (reset) state<=s0;
else state<=next_state;
end
always @(posedge clk)
begin
if (reset) temp<=9'd0;
else temp<={in,temp[8:1]};
end
assign done=(state==s10);
assign out_byte=done?temp[7:0]:10'd0;
endmodule
