HDLbits：Lemmings4

这道题目并不难，我想的太难了。只需要在前一道题目的基础上做下面几个步骤:

1、lemming多加一个状态DEAD

2、加一个always块记录下落时间

3、把这个下落时间引入到FALLING落地状态转换的判断里

PS：容易出错的地方：1、计数器到达19是完整的20s时间 2、不仅重置的时候计数器需要清零，除了下落之外的其他状态也要清零。

module top_module(
    input clk,
    input areset,    // Freshly brainwashed Lemmings walk left.
    input bump_left,
    input bump_right,
    input ground,
    input dig,
    output walk_left,
    output walk_right,
    output aaah,
    output digging ); 
    
    
    parameter LEFT=7'b0000001, RIGHT=7'b0000010, LEFT_FALLING=7'b0000100, RIGHT_FALLING=7'b0001000, 
        LEFT_DIGGING=7'b0010000, RIGHT_DIGGING=7'b0100000, DEAD=7'b1000000, DEAD_TIME=32'd19;
        
    reg [6:0] state,next_state;
    
    reg [31:0] falltime_counter;

    always@(*)begin
        case(state)
            LEFT: next_state = ground?(dig?LEFT_DIGGING:(bump_left?RIGHT:LEFT)):LEFT_FALLING;                    
            RIGHT: next_state = ground?(dig?RIGHT_DIGGING:(bump_right?LEFT:RIGHT)):RIGHT_FALLING;  
            LEFT_FALLING: next_state = ground?(falltime_counter>DEAD_TIME?DEAD:LEFT):LEFT_FALLING;
            RIGHT_FALLING: next_state = ground?(falltime_counter>DEAD_TIME?DEAD:RIGHT):RIGHT_FALLING;
            LEFT_DIGGING: next_state = ground?LEFT_DIGGING:LEFT_FALLING;
            RIGHT_DIGGING: next_state = ground?RIGHT_DIGGING:RIGHT_FALLING;
            DEAD: next_state = DEAD;
            default: next_state = LEFT;
        endcase            
    end
    
    always@(posedge clk or posedge areset)begin
        if(areset)
          state <= LEFT;
        else
          state <= next_state;
    end
    
    always@(posedge clk or posedge areset )begin
        if(areset)
           falltime_counter <= 0;
        else if(state == RIGHT_FALLING || state == LEFT_FALLING)
           falltime_counter <= falltime_counter + 1;
        else
           falltime_counter <= 0;
    end
    
    assign walk_left = (state == LEFT);
    assign walk_right = (state == RIGHT);
    assign aaah = (state == LEFT_FALLING || state == RIGHT_FALLING);
    assign digging = (state == RIGHT_DIGGING || state == LEFT_DIGGING);    
    
endmodule