HDLbits 记录_Q130 FSM ps2data

相当于对上一题的状态机[HDLbits 记录_Q128 Fsm onehot]增加了输出的逻辑，即将三个byte接收之后以out_byte[23:0]的格式打出，同时done信号作为数据有效信号输出。

 题目比较简单，在上一题的状态机基础上增加移位寄存器和输出逻辑即可，直接贴上代码

module top_module(
    input clk,
    input [7:0] in,
    input reset,    // Synchronous reset
    output [23:0] out_bytes,
    output done); //

    // FSM from fsm_ps2
	parameter	IDLE = 2'd1;
    parameter	SYN = 2'd2;
    parameter	DONE = 2'd3;
    
    reg		[1:0] 	curr_state;
    reg		[1:0]	next_state;
    reg		[1:0]	syn_cnt;
    reg		[23:0]	out_reg;
    
    assign	out_bytes = out_reg;
    // State transition logic (combinational)
    always @(posedge clk) begin
        if(reset == 1'b1) begin
        	curr_state <= IDLE;    
        end
        else begin
        	curr_state <= next_state;     
        end
    end
    // State flip-flops (sequential)
    always @(*) begin
        case(curr_state)
           IDLE: begin
               if(in[3] == 1'b1) begin
                  next_state = SYN; 
               end
               else begin
                  next_state = IDLE;
               end
           end
           SYN: begin
               if(syn_cnt >= 2'd1) begin
                  next_state = DONE;
               end
               else begin
                  next_state = SYN; 
               end
           end
            DONE:begin
               if(in[3] == 1'b1) begin
                  next_state = SYN; 
               end
               else begin
                  next_state = IDLE;
               end
            end
            default: next_state = IDLE;
        endcase
    end
    // Output logic
    always @(posedge clk) begin
        if(reset == 1'b1) begin
            syn_cnt <= 2'd0;
        end
        else if(curr_state == SYN) begin
            syn_cnt <= syn_cnt +1'd1;
        end
        else begin
            syn_cnt <= 2'b0;
        end
    end
    assign done = (curr_state == DONE)?1:0;
    // New: Datapath to store incoming bytes.
    always @(posedge clk) begin
        if(reset == 1'b1) begin
           out_reg <= 24'b0; 
        end
        else begin
            out_reg <= {out_reg[16:0],in}; 
        end
    end
    
endmodule