HDLBits之Exams/2014 q3fsm

Consider a finite state machine with inputs s and w. Assume that the FSM begins in a reset state called A, as depicted below. The FSM remains in state A as long as s = 0, and it moves to state B when s = 1. Once in state B the FSM examines the value of the input w in the next three clock cycles. If w = 1 in exactly two of these clock cycles, then the FSM has to set an output z to 1 in the following clock cycle. Otherwise z has to be 0. The FSM continues checking w for the next three clock cycles, and so on. The timing diagram below illustrates the required values of z for different values of w.

Use as few states as possible. Note that the s input is used only in state A, so you need to consider just the w input.

解析：没有想到利用两个计数器，第一个计时钟，第二个计w的状态。

代码：

module top_module (
    input clk,
    input reset,   // Synchronous reset
    input s,
    input w,
    output z
);
    parameter A=0;
    parameter B=1;
    reg c_state,n_state;
    always@(posedge clk)begin
        if(reset)
            c_state<=A;
        else
            c_state<=n_state;
    end
    always@(*)begin
        case(c_state)
            A:n_state=s?B:A;
            B:n_state=B;
        endcase
    end
    reg [1:0]cnt1,cnt2;
    always@(posedge clk)begin
        if(reset)begin
            cnt1<=0;
        end
        else if(c_state==B)begin
            if(cnt1==2'd2)
                cnt1<=0;
            else
                cnt1<=cnt1+1'b1;
        end
    end
    always@(posedge clk)begin
        if(reset)begin
            cnt2<=0;
        end
        else if(c_state==B)begin
            if(cnt1==2'd0)
                cnt2<=w; 
            else if(w)
                cnt2<=cnt2+1'b1;
        end
    end
    
    assign z=(c_state==B&&cnt1==2'd0&&cnt2==2'd2); 
endmodule