【HDLBits】Fsm serialdata笔记

Now that you have a finite state machine that can identify when bytes are correctly received in a serial bitstream, add a datapath that will output the correctly-received data byte. out_byte needs to be valid when done is 1, and is don't-care otherwise.

Note that the serial protocol sends the least significant bit first.

Some timing diagrams

Error-free:

module top_module(
    input clk,
    input in,
    input reset,    // Synchronous reset
    output [7:0] out_byte,
    output done
); //
    parameter  idle=0, start=1, data=2, stop=3, error=4;
    reg  [2: 0] state, next_state;
    reg  [3: 0] count;
    reg  [7: 0] store;
    // Use FSM from Fsm_serial
    always @(*)
        begin
            case(state)
                idle:  next_state = in ? idle: start;
                start: next_state = data;
                data:  next_state = count == 4'd8 ? ( in ? stop: error): data;
                stop:  next_state = in ? idle: start;
                error: next_state = in ? idle: error;
            endcase
        end
    
    always @(posedge clk)
        begin
            if (reset)
                begin
                    state <= 3'b0;
                    count <= 4'b0;
                    store <= 8'b0;
                end
            else
                begin
                    state <= next_state;
                    count <= 4'b0;
                    done  <= 1'b0;
                    if(next_state == data)
                        begin
                            count <= count +1'b1;
                            store <= {in, store[7:1]};
                        end
               
                    if(next_state == stop)
                        begin
                            done <= 1'b1;
                            out_byte <= store;
                        end
          
                end
        end
    // New: Datapath to latch input bits.
    

endmodule
 

对于时钟边沿触发下，进行计数等操作，采用next_state而不是state将不会存在状态与计数操作差一个时钟周期的问题，不会使得判断输出done信号的出错。！！！！