FPGA顶层模块设计
`include"param.v"
module ov5640_sdram_vga (
input clk ,
input rst_n ,
//ov5640 port
input cmos_vsync ,
input cmos_href ,
input [7:0] cmos_din ,
input cmos_pclk ,
output cmos_xclk ,
output cmos_pwdn ,
output cmos_reset ,
output cmos_sioc ,
inout cmos_siod ,
//sdram port
output [12:0] sdram_addr ,//行、列地址
output [1:0] sdram_bank ,
output sdram_clk ,
output sdram_cke ,
output sdram_rasn ,
output sdram_casn ,
output sdram_csn ,
output sdram_wen ,
output [1:0] sdram_dqm ,
inout [15:0] sdram_dq ,
//vga port
output vga_hsync ,
output vga_vsync ,
output [15:0] vga_rgb
);
//信号定义
wire clk_24m ;
wire clk_100m ;
wire clk_200m ;
wire clk_100m_s ;
wire clk_vga ;
wire cfg_done ;
wire pclk ;
wire [15:0] pixel ;
wire pixel_vld ;
wire pixel_sop ;
wire pixel_eop ;
wire [15:0] mem_din ;
wire mem_din_vld ;
wire mem_din_sop ;
wire mem_din_eop ;
wire [15:0] vga_data ;
wire vga_data_vld;
wire vga_req ;
wire vga_rst ;
assign vga_rst = rst_n & cfg_done;
//模块例化
pll u_pll (
.areset (~rst_n ),
.inclk0 (clk ),
.c0 (clk_24m ),
.c1 (clk_100m ),
.c2 (clk_vga ),
.c3 (clk_200m ),//signaltap采样时钟
.c4 (clk_100m_s ) //100m 相位偏移75度
);
iobuf u_iobuf(
.datain (cmos_pclk ),
.dataout (pclk )
);
`ifdef ONE_SLAVE //i2c接口和cfg模块直接握手
ov5640_config u_cfg(
/*input */.clk (clk ),
/*input */.rst_n (rst_n ),
//摄像头接口
/*output */.sio_c (cmos_sioc ),
/*inout */.sio_d (cmos_siod ),
/*output */.cfg_done(cfg_done ) //初始化配置完成
);
`elsif
ov5640_cfg u_cfg( //使用双buf模式
/*input */.clk (clk ),
/*input */.rst_n (rst_n ),
//摄像头接口
/*output */.sio_c (cmos_sioc ),
/*inout */.sio_d (cmos_siod ),
/*output */.cfg_done(cfg_done ) //初始化配置完成
);
`endif
capture u_capture(
/*input */.clk (pclk ), //pclk
/*input */.rst_n (rst_n ),
/*input [7:0] */.cmos_din (cmos_din ),
/*input */.cmos_vsync (cmos_vsync ),
/*input */.cmos_href (cmos_href ),
/*input */.cap_en (cfg_done ),//采集使能信号
/*output [15:0] */.pixel (pixel ),
/*output */.pixel_vld (pixel_vld ),
/*output */.pixel_sop (pixel_sop ),//数据包文头
/*output */.pixel_eop (pixel_eop ) //数据包文尾
);
`ifdef ENABLE_EDGE_DETECT
wire [15:0] img_din ;
wire img_din_vld ;
wire img_din_sop ;
wire img_din_eop ;
wire [15:0] imp_dout ;
wire imp_dout_vld ;
wire imp_dout_sop ;
wire imp_dout_eop ;
assign img_din = pixel ;
assign img_din_vld = pixel_vld ;
assign img_din_sop = pixel_sop ;
assign img_din_eop = pixel_eop ;
assign mem_din = imp_dout ;
assign mem_din_vld = imp_dout_vld;
assign mem_din_sop = imp_dout_sop;
assign mem_din_eop = imp_dout_eop;
img_process u_img_process(
/*input */.clk (pclk ),
/*input */.rst_n (rst_n ),
/*input [15:0] */.din (img_din ),
/*input */.din_vld (img_din_vld ),
/*input */.din_sop (img_din_sop ),
/*input */.din_eop (img_din_eop ),
/*output [15:0] */.dout (imp_dout ),
/*output */.dout_vld (imp_dout_vld ),
/*output */.dout_sop (imp_dout_sop ),
/*output */.dout_eop (imp_dout_eop )
);
`elsif
assign mem_din = pixel ;
assign mem_din_vld = pixel_vld;
assign mem_din_sop = pixel_sop;
assign mem_din_eop = pixel_eop;
`endif
sdram_controler u_sdram_ctrl(
/*input */.clk (clk_100m ),
/*input */.clk_in (pclk ),
/*input */.clk_out (clk_vga ),
/*input */.rst_n (rst_n ),
//用户输入
/*input */.rd_en (vga_req ),
/*input [15:0] */.din (mem_din ),
/*input */.din_vld (mem_din_vld ),
/*input */.din_sop (mem_din_sop ),
/*input */.din_eop (mem_din_eop ),
/*output [15:0] */.dout (vga_data ),
/*output */.dout_vld (vga_data_vld ),
//sdram接口
//output sdram_clk ,
/*output */.sdram_cke (sdram_cke ),
/*output */.sdram_csn (sdram_csn ),
/*output */.sdram_rasn (sdram_rasn ),
/*output */.sdram_casn (sdram_casn ),
/*output */.sdram_wen (sdram_wen ),
/*output [1:0] */.sdram_bank (sdram_bank ),
/*output [12:0] */.sdram_addr (sdram_addr ),
/*inout [15:0] */.sdram_dq (sdram_dq ),
/*output [1:0] */.sdram_dqm (sdram_dqm )
);
vga_intf u_vga_intf(
/*input */.clk (clk_vga ),
/*input */.rst_n (vga_rst ),
/*input [15:0] */.din (vga_data ),
/*input */.din_vld (vga_data_vld ),
/*output */.req (vga_req ),
/*output */.vsync (vga_vsync ),
/*output */.hsync (vga_hsync ),
/*output [15:0] */.rgb (vga_rgb )
);
assign cmos_pwdn = 1'b0;
assign cmos_reset = 1'b1;
assign cmos_xclk = clk_24m;
assign sdram_clk = ~clk_100m;
endmodule参数定义文件
//定义一个摄像头
`define ONE_SLAVE
//定义是否使用边缘检测模式
//`define ENABLE_EDGE_DETECT
//OV5640配置部分参数
//define REG_NUM 254 //定义需要配置的寄存器个数 输出内置彩条
`define REG_NUM 252 //定义需要配置的寄存器个数 输出采集的数据
`define WRITE_ONLY //定义只写寄存器
//`define WRITE_READ //定义先写再读寄存器
`ifdef WRITE_ONLY
`define RD_FLAG 1'b0 //读寄存器标志参数
`elsif WRITE_READ
`define RD_FLAG 1'b1
`endif
`define WR_ID 8'h78 //写摄像头ID
`define RD_ID 8'h79 //读摄像头ID
//I2C时钟参数
`define SCL_MAX 150 //I2C时钟周期
`define SCL_HALF 75 //I2C时钟翻转时间
`define SEND 25 //发送数据时间
`define SAMPLE 115 //采样数据时间
//i2c_intf命令
`define CMD_START 4'b0001 //发起始位命令码
`define CMD_WR 4'b0010 //写1字节数据
`define CMD_RD 4'b0100 //读1字节数据
`define CMD_STOP 4'b1000 //发停止位
//定义图像分辨率
`define IMG_W 1280
`define IMG_H 720
//sdram参数
//`define BL_1
//`define BL_2
//`define BL_4
//`define BL_8
`define BL_FULL
`ifdef BL_1 //定义模式寄存器的突发长度
`define BL 3'b000
`define BURST_LEN 1
`elsif BL_2
`define BL 3'b001
`define BURST_LEN 2
`elsif BL_4
`define BL 3'b010
`define BURST_LEN 4
`elsif BL_8
`define BL 3'b011
`define BURST_LEN 8
`elsif BL_FULL
`define BL 3'b111
`define BURST_LEN 512
`endif
`define BURST_MAX `IMG_W*`IMG_H //定义最大突发地址
`define SEQ_BURST
//`define INT_BURST
`ifdef SEQ_BURST //定义模式寄存器的突发类型
`define BT 1'b0
`elsif INT_BURST
`define BT 1'b1
`endif
`define CASL_2
//`define CASL_3
`ifdef CASL_2 //定义模式寄存器的列选通延时
`define CASL 3'b010
`elsif CASL_3
`define CASL 3'b011
`endif
`define OP_0
`define OP_1
`ifdef OP_0 //定义模式寄存器的突发模式
`define OP_CODE 1'b0
`elsif OP_1
`define OP_CODE 1'b1
`endif
//时间参数定义
`define TWAIT 20000
`define TRRC 7
`define TRCD 3
`define TRP 3
`define TMRS 3
`define TREF 780
//命令参数
`define CMD_PRECH 4'b0010
`define CMD_AREF 4'b0001
`define CMD_MRS 4'b0000
`define CMD_ACTI 4'b0011
`define CMD_WRITE 4'b0100
`define CMD_READ 4'b0101
`define CMD_NOP 4'b0111
`define WR_TH 512
`define RD_TH_L 600
`define RD_TH_U 1500
//VGA时序参数
//行同步时序 单位：vga像素时钟周期
`define H_SYNC 40
`define H_BP 220
`define H_ACT 1280
`define H_FP 110
`define H_TOTAL 1650
//场同步时序 单位：一行
`define V_SYNC 5
`define V_BP 20
`define V_ACT 720
`define V_FP 5
`define V_TOTAL 750