数电和Verilog-时序逻辑实例二：移位寄存器

A.15 时序逻辑实例二：移位寄存器

简单的单向移位寄存器，由低位向高位移动，可以通过load加载设定移位寄存器的初始值。

设计模块

//文件路径：a.15/src/shifter.v
module shifter(clk,rst_n,load_enable,load_data,dout);
  input clk;
  input rst_n;
  input load_enable;
  input[7:0] load_data;
  output[7:0] dout;

  reg[7:0] shift_data;

  always@(posedge clk)begin
    if(!rst_n)
      shift_data <= 'd0;
    else begin
      if(load_enable)
        shift_data <= load_data;
      else
        shift_data <= {shift_data[6:0],shift_data[7]};
    end
  end

  assign dout = shift_data;

endmodule

测试模块

//文件路径：a.15/sim/testbench/demo_tb.sv
module top;
  logic clk;
  logic rst_n;
  logic load_enable;
  logic[7:0] load_data;
  logic[7:0] dout;
  
  shifter DUT(.clk(clk),.rst_n(rst_n),.load_enable(load_enable),.load_data(load_data),.dout(dout));

  initial begin
    clk = 0;
    forever begin
      #10;
      clk = ~clk;
    end
  end

  initial begin
    rst_n = 0;
    #50;
    rst_n = 1;
  end

  initial begin
    $display("%t -> Start!!!",$time);
    load_enable = 0;
    load_data = 0;
    #100;

    load_enable = 1;
    std::randomize(load_data);
    $display("%t -> load_data is %b",$time,load_data);
    #100;

    load_enable = 0;

    #300;
    $display("%t -> Finish!!!",$time);
    $finish;
  end 

endmodule : top

仿真结果

运行./run.do脚本后，查看仿真日志sim.log，然后打开dve查看波形。

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