AARCH64 常用的指令和寄存器描述

• 当我们在写汇编时要参考什么

1. ABI
	// 当考虑了ABI之后,这样子写的汇编代码就可以和C代码兼容,可以相互调用
3. 语法 (指令解释中的各种概念是什么)
	// C1.2 Structure of the A64 assembler language
	// C2.1 Understanding the A64 instruction descriptions
	// C6.2 Alphabetical list of A64 base instructions
4. 该指令是否会影响其他的东西
	// C6.1 About the A64 base instructions
		1. PSTATE
		2. PC
		3. SP
5. 指令中的地址 寻址方式是什么
	// C1.3 Address generation
6. 想要用的指令在哪个类
	// C3 A64 Instruction Set Overview
7. 指令如何编码
	// C4 A64 Instruction Set Encoding
8. 是否为特权指令
	// C5 The A64 System Instruction Class
9. 是否为SIMD&FP指令
	// C7 A64 Advanced SIMD and Floating-point Instruction Descriptions

• 基础知识

有效VA范围由以下因素决定：
	• 实现的虚拟地址空间的大小。 由 内存管理单元MMU 相关寄存器配置设置。
		TCR.T1SZ
		TCR.T0SZ
	ARMv8-A架构下,它的低位有效位数(也就是虚拟地址空间大小),是可以配置的,最大48位,最小12位. 
	不过,为了方便页表的对齐,我们通常会设置一些特定的位数.比如48,39,30.
	在代码中,你可以看到有关T0SZ,T1SZ的设置,就是用来配置这个项目的. 
	有效位数为64-TxSZ (或者,也可以说TxSZ是用来设置高位无效位数的)

The only instructions that can read the PC are those that generate a PC relative address:
	• ADR and ADRP.
	• The Load register (literal) instruction class.
	• Direct branches that use an immediate offset.
	• The unconditional branch with link instructions, BL and BLR, that use the PC to create the return link address.


Only explicit control flow instructions can modify the PC:

	• Conditional and unconditional branch and return instructions.
	• Exception generation and exception return instructions.

以 SP 作为输入

A64 instructions can use the stack pointer only in a limited number of cases:


• Load/Store instructions use the current stack pointer as the base address: 
	— When stack alignment checking is enabled by system software and the base register is SP, the current stack pointer must be initially quadword aligned, 
	That is, it must be aligned to 16 bytes. Misalignment generates an SP alignment fault. See SP alignment checking on page D1-2287 for more information. 
• Add and subtract data processing instructions in their immediate and extended register forms, use the current stack pointer as a source register or the destination register or both.


• Logical data processing instructions in their immediate form use the current stack pointer as the destination register.

以 PSTATE 作为输出


The A64 base instructions that use the Condition flags as an input are:


	• Conditional branch. The conditional branch instruction is B.cond .


	• Add or subtract with carry. These instruction types include instructions to perform multi-precision arithmetic and calculate checksums. The add or subtract with carry instructions are ADC , ADCS , SBC , and SBCS , or an architectural alias for these instructions.


	• Conditional select with increment, negate, or invert.This instruction type conditionally selects between one source register and a second, incremented, negated, inverted, or unmodified source register. The conditional select with increment, negate, or invert instructions are CSINC , CSINV , and CSNEG .

	These instructions also implement:


	— Conditional select or move. The Condition flags select one of two source registers as the destination register. Short conditional sequences can be replaced by unconditional instructions followed by a conditional select, CSEL .


	— Conditional set. Conditionally selects between 0 and 1, or 0 and -1. This can be used to convert the Condition flags to a Boolean value or mask in a general-purpose register, for example. These instructions include CSET and CSETM .


	• Conditional compare. This instruction type sets the Condition flags to the result of a comparison if the original condition is true, otherwise it sets the Condition flags to an immediate value. It permits the flattening of nested conditional expressions without using conditional branches or performing Boolean arithmetic within the general-purpose registers.The conditional compare instructions are CCMP and CCMN .


以 PSTATE 作为输出

The A64 base instructions that update the Condition flags as an output are:


	• Flag-setting data processing instructions, such as ADCS , ADDS , ANDS , BICS , RMIF , SBCS , SETF8 , SETF16 , and SUBS , and the aliases CMN , CMP , and TST .


	• Conditional compare instructions such as CCMN , CCMP .


	• The random number generation instructions MRS RNDR and MRS RNDRRS , see Effect of random number generation instructions on Condition flags on page C6-752.


直接改变 PSTATE

The A64 base instructions that manipulate the Condition flags are: 
	• The flag manipulation instruction CFINV , which inverts the value of the Carry flag.

	A64 Base Instruction Descriptions 
	• If ARMv8.5-CondM is implemented, the base instructions AXFLAG and XAFLAG . These instructions convert between the Arm floating point comparison PSTATE condition flag format and an alternative format shown in Table C6-1.

	The flags can be directly accessed for a read/write using the NZCV, Condition Flags on page C5-400.

	The A64 base instructions also include conditional branch instructions that do not use the Condition flags as an input: 
	• Compare and branch if a register is zero or nonzero, CBZ and CBNZ .


	• Test a single bit in a register and branch if the bit is zero or nonzero, TBZ and TBNZ .






Effect of random number generation instructions on Condition flags 

	If ARMv8.5-RNG is implemented, then: 
	• When a valid random number is returned, the PSTATE.NZCV flags are set to 0b0000 .


	• If the random number hardware is not capable of returning a random number in a reasonable period of time, the PSTATE.NZCV flags are set to 0b0100 , and the random number generation instructions return the value 0.


	Note 

		The definition of “reasonable period of time” is IMPLEMENTATION DEFINED . The expectation is that software might use this as an opportunity to reschedule or run a different routine, perhaps after a small number of retries have failed to return a valid value.value.

• EL0/1常用的 A64 指令

.inst	// 伪指令 , 表示这条指令不对应任何指令,为未定义指令
.word	// 伪指令 , 在当前位置放一个word型的值

add		// 三种变体1.extended register 2. immediate 3.shifted register
adrp	// base = PC[11:0]=ZERO(12); Xd = base + label;
and		// 两种变体1.immediate 2.shifted register
asr		// 两种变体1.register 2.immediate // Arithmetic Shift Right 
b
b.cc	// 属于 B.cond , cond 取自 P173
b.cs
b.eq
b.ge
b.gt
b.hi
b.le
b.ls
b.lt
b.ne
bl		// Branch with Link branches to a PC-relative offset
blr		// Branch with Link to Register calls a subroutine at an address in a register, setting register X30 to PC+4
brk		// 进入debug异常
cmn		// 加,更新PSTATE
cmp 	// 减,更新PSTATE
cneg	// Conditional Negate returns ,根据条件返回两个值中的一个或另一个的负数
csel	// Conditional Select returns
cset	// Conditional Set
eret	// 用于异常返回
ldp		// Load Pair of Registers
ldr		// Load Register
ldrb	// Load Register Byte
ldrh	// Load Register Halfword
ldrsw	// Load Register Signed Word 
lsl		// Logical Shift Left
lsr		// Logical Shift Right
mov		// Move between register and stack pointer
movk	// Move wide with keep moves an optionally-shifted 16-bit immediate value into a register, keeping other bits unchanged.
mrs		// move sytem register value to general-purpose register
msr		// move general-purpose register value to sytem register
mul		// Multiply : Rd = Rn * Rm
neg		// Negate (shifted register) negates an optionally-shifted register value, and writes the result to the destination register.
nop		// No Operation does nothing, other than advance the value of the program counter by 4. 
orr		// Bitwise OR (immediate) performs a bitwise (inclusive) OR of a register value and an immediate register value, and writes the result to the destination register.
ret		// Return from subroutine branches unconditionally to an address in a register, with a hint that this is a subroutine return.
smull	// Signed Multiply Long multiplies two 32-bit register values, and writes the result to the 64-bit destination register.
stp		// Store Pair of Registers calculates an address from a base register value and an immediate offset, and stores two 32-bit words or two 64-bit doublewords to the calculated address, from two registers. For information about memory accesses
str		// Store Register 
strb
strh
stur 	// Store Register (unscaled) calculates an address from a base register value and an immediate offset
sub		// Subtract (extended register) subtracts a sign or zero-extended register value
svc		// 进入svc异常
sxtb	// Signed Extend Byte extracts an 8-bit value from a register,
sxth
sxtw
udiv	// Unsigned Divide divides an unsigned integer register value by another unsigned integer register value
umull	// Unsigned Multiply Long multiplies two 32-bit register values, and writes the result to the 64-bit destination register.
wfi		// Wait For Interrupt is a hint instruction that indicates that the PE can enter a low-power state and remain there until a wakeup event occurs. For more information

• EL0/1常用的寄存器

// K14 Registers Index P7809

// 这里面比较特殊的寄存器 有 SP/PC/PSTATE(及其相关的域寄存器)
// 这些寄存器会被执行的指令隐式改变,而其他寄存器不会被隐式改变,只会被显式改变

通用寄存器（31个）// D1.6.1 The general purpose registers, R0-R30 P2277
	X0 - X30 // P99 B1.2.1 Registers in AArch64 state
SIMD&FP registers(32个+2)
	V0 - V31
PC寄存器
	PC
状态寄存器(1个) // D1.7 Process state, PSTATE P2284
	PSTATE // 不能被直接访问
特殊寄存器（27个）// C5.2 Special-purpose registers P347 // 默认不能被EL0访问,除非有特殊声明
	• CurrentEL, that holds PSTATE.EL, and that software can read to determine the current Exception level.
	• DAIF, that holds the current PSTATE.{D, A, I, F} interrupt mask bits.
		// 能不能被 EL0 访问, 取决于 SCTLR_EL1.UMA 的设置
	• DIT, that holds the PSTATE.DIT bit.
	• NZCV, that holds the PSTATE.{N, Z, C, V} condition flags.
		// 一直能被 EL0 访问
	• PAN, that holds the PSTATE.PAN state bit.
	• SPSel, that holds PSTATE.SP, that at EL1 or higher selects the current SP.
	• SSBS, that holds the PSTATE.SSBS bit.
	• TCO, that holds the PSTATE.TCO bit.
	• UAO, that holds the PSTATE.UAO bit.

	• ELR_EL1, that holds the address to return to for an exception return from EL1.
	• SPSR_EL1, that holds process state on taking an exception to AArch64 EL1.
	
	• FPCR, that provides control of floating-point operation.
	• FPSR, that provides floating-point status information.
	
	• SP_EL0, that holds the stack pointer for EL0.
	• SP_EL1, that holds the stack pointer for EL1.

	• DLR_EL0, that holds the address to return to for a return from Debug state.
	• DSPSR_EL0, that holds process state on entry to Debug state