【初学者】FPGA中时钟和时序的概念（未完）

视频：FPGA Clock and timing concepts explained simply for beginners using two analogies!

The FPGA takes signals in or data in and it processes it a little bit at a time until we procude an output. It's one of the core fundamental things that the FPGA is used for and the benefit. FPGA has the benefit of being able to quickly and easily process with different samples over and over again in the same way.（FPGA 接收信号或数据，并一次处理一点点，直到产生输出。 这是 FPGA 的用途和优势。 FPGA 的优点是能够以相同的方式快速、轻松地反复处理不同的样本。）

FPGA is like a conveyor belt in the factory, it's moving at a specific rate through our factory. The clock is the tempo by which we process samples in the FPGA and if we have a faster clock then our conveyor belt is moving faster and our samples are moving faster and if we have a slow clock then our conveyor belt is moving slower and our samples are moving slower. （FPGA 好似工厂里的传送带，传送带以特定的速度穿过我们的工厂。 时钟clock是我们在 FPGA 中处理样本的速度，如果我们有更快的时钟，那么我们的传送带移动得更快，我们的样本移动得更快；如果我们有慢时钟，那么我们的传送带移动得更慢，我们的样本也移动得更快。 移动速度较慢。）

一、FPGA类比工厂流水线

In our case we're going to be saying that a sample is on every clock cycle, but that is not always the case in factories and in FPGAs. You can have time where maybe this conveyor belt is empty, and you can have times where the FPGA's clock contains an empty or not valid sample.（在我们的例子中，我们认为每个时钟周期都有一个样本，但在工厂和 FPGA 中情况并非总是如此。 有时传送带可能是空的，有时 FPGA 时钟包含空样本或无效样本。）

But for the purposes of our discussion, we're going to be assuming that every single clock cycle is a valid sample but that's not always the case. If you think about a factory setting where maybe you have a station and a worker is performing a job. So say for example it's a toothpaste factory and the worker is putting the lids on the toothpaste tube and if you have a slow clock and a slow conveyor belt then the worker has lots of time to put his lid on his toothpaste tube. But what if it's really quick, what if the conveyor belt is moving really quickly and now he's got a hurry so the rate of the clock or the rate of the conveyor belt can make a big difference whether the tasks on the FPGA or the tasks that the worker needs to perform can be accomplished in time or not. （但出于我们讨论的目的，我们将假设每个时钟周期都是有效样本，但情况并非总是如此。 如果考虑一下工厂环境，那里可能有一个工作站并且一名工人正在执行工作。 举例来说，有一家牙膏工厂，工人正在给牙膏管盖上盖子，如果你有一个慢速传送带，那么工人就有很多时间将盖子盖上牙膏管。 但是，如果传送带移动得非常快，工人很着急，那么传送带的速率将会带来很大影响，无论是 FPGA 上的任务还是现场运行的任务。 工人需要执行的任务可以及时完成，也可以不完成。）

And if you've heard the word timing analysis or meeting timing or time enclosure, that's what that is. That is does the FPGA have time or does the worker have time to do his allotted task before the next sample comes along. And if your FPGA meets time enclosure, then it means yes he does have enough time, the FPGA does have enough time to perform their tasks that need to be done but if it doesn't meet time enclosure then it means that our poor worker can't keep up.（“时序分析”或“会议时序”或“时间范围”，就是在下一个样本出现之前，FPGA 是否有时间或者工作人员是否有时间完成分配的任务。如果FPGA满足时间范围，就意味着FPGA有足够的时间来执行需要完成的任务，但如果它不满足时间范围，就好比工人跟不上生产速度。）

Or maybe one day his manager comes along and says now you also have to put the toothpaste tube in the box and then only are you done. And suddenly what was easy to do and he had lots of time to put the lid on now he's running around and rushing because he's got to put it in the box and put it over there as well and now what was enough time suddenly isn't enough time. （或者有一天，你的经理过来告诉你，除了拧盖子，现在你还必须把牙膏管放进盒子里。 突然之间，本来很容易做的事情，本来有很多时间盖上盖子，但是现在他必须把它放进盒子里，突然没有足够的时间了。 ）

And so these concepts in the FPGA can be quite abstract. But if we use the analogy of a factory it does actually work quite well to understand intuitively timing concepts that can be quite complicated. And that's why a lot of the time if you're failing to meet time enclosure, if your workers are failing to be able to do their jobs. The 2 main things that you do is you add pipelining, you put in more workers or you slow your clock down. And depending on your application one or both will be necessary and as time goes on and you gain a little bit more experience, you'll get a better intuition for how much work every worker can do for a specific clock rate and as the clock rate goes up, their ability to do their work gets smaller because they have less time, and so this is important to keep in mind and as we go into clocking and learning these other concepts to remember in the back of your mind.（FPGA 中的这些概念可能非常抽象。 但如果我们使用工厂作为类比，可以更好地理解timing的概念。 很多时候你无法满足时间限制，如果工厂的员工无法完成他们的工作，管理者要做的两件事是添加pipeline、投入更多工作人员或者减慢时钟速度。 根据你的应用程序，其中一个或两个都是必要的，随着时间的推移，您获得更多的经验，您将更好地更直观地了解每个工作人员在特定时钟速率下可以完成多少工作，以及随着时钟速率的上升，他们完成工作的能力会变弱，因为他们的时间更少。这就是FPGA中有关时钟的概念，我们需要经验的积累，去更好地设置FPGA的时钟。）

二、FPGA类比定格电影