设计一抢答器,要求如下:抢答台数为6;具有抢答开始后20s倒计时,20秒倒计时后6人抢答显示超时,并报警;能显示超前抢答台号并显示犯规报警;系统复位后进入抢答状态,当有一路抢答按键按下,该路抢答信号将其余各路抢答信号封锁,同时铃声响起,直至该路按键松开,显示牌显示该路抢答台号。
clk时钟信号
b1~b6抢答按钮
reset复位按钮
shield屏蔽标志位
stop倒计时暂停标志位
show显示器
alarm1报警信号(1超时,2抢答,3正常抢答)
1、主模块代码
module RaceMain(clk,reset,t,b1,b2,b3,b4,b5,b6,alarm1,show);
input clk,reset,b1,b2,b3,b4,b5,b6;
output[5:0] t;
output[1:0] alarm1;
output[3:0] show;
reg[5:0] t=0;
reg[1:0] alarm1=0;
reg[3:0] show=0;
reg[1:0] sheild=0;
reg[1:0] stop=0;
/
always @(reset,b1,b2,b3,b4,b5,b6)
begin
if(reset)
begin
if(b1|b2|b3|b4|b5|b6==1)
stop=1;
end
else
stop=0;
end
/count down
always @(posedge clk)
begin
if(~reset)
t<=20;
else
if(stop==0)
begin
if(t==1||t==0)
t<=0;
else
t<=t-1;
end
end
/illegality
always @(b1,b2,b3,b4,b5,b6,reset)
begin
if(~reset)
begin
if(b1==1)show<=1;
if(b2==1)show<=2;
if(b3==1)show<=3;
if(b4==1)show<=4;
if(b5==1)show<=5;
if(b6==1)show<=6;
if(b1|b2|b3|b4|b5|b6==1)alarm1<=1;
end
end
/overtime
always @(b1,b2,b3,b4,b5,b6,reset,t)
begin
if(reset==1&&t==0&&b1==0&&b2==0&&b3==0&&b4==0&&b5==0&&b6==0)
alarm1<=2;
end
/have rushed to answer
/signal shielding
always @(b1,b2,b3,b4,b5,b6,reset,t,sheild)
begin
if(reset==1&&t!=0&&(b1==1||b2==1||b3==1||b4==1||b5==1||b6==1)&&sheild==0)
begin
alarm1<=3;
sheild<=1;
end
end
on the responder
always @(b1,b2,b3,b4,b5,b6,reset,t)
begin
if(reset==1&&t!=0&&(b1==1||b2==1||b3==1||b4==1||b5==1||b6==1)&&sheild==0)
begin
case({b1,b2,b3,b4,b5,b6})
6'b100000:show<=1;
6'b010000:show<=2;
6'b001000:show<=3;
6'b000100:show<=4;
6'b000010:show<=5;
6'b000001:show<=6;
default:show<=0;
endcase
end
end
/
always @(negedge reset)
begin
show<=0;
alarm1<=0;
stop<=0;
sheild<=0;
end
endmodule
测试模块代码:
module RaceTest;
reg clk,reset,b1,b2,b3,b4,b5,b6;
wire[5:0] t;
wire[1:0] alarm1;
wire[3:0] show;
RaceMain u1(.clk(clk),.reset(reset),.t(t),.b1(b1),.b2(b2),.b3(b3),.b4(b4),.b5(b5),.b6(b6),.alarm1(alarm1),.show(show));
always
#10 clk=~clk;
initial
begin
clk=0;reset=0;b1=0;b2=0;b3=0;b4=0;b5=0;b6=0;
over time test
#100 reset=1;
#500 reset=0;
illegality test
#50 b3=1;
#10 b3=0;
#50 b4=1;
#10 b4=0;
have rushed to answer and signal shielding test
#100 reset=1;
#10 b5=1;
#10 b6=1;
#10 b5=0;
#10 b6=0;
#100 reset=0;
end
endmodule