Verilog刷题笔记18

题目：An if statement usually creates a 2-to-1 multiplexer, selecting one input if the condition is true, and the other input if the condition is false.

解题：

module top_module(
    input a,
    input b,
    input sel_b1,
    input sel_b2,
    output wire out_assign,
    output reg out_always   ); 
	
    always @(*)begin
        if (sel_b1==1&&sel_b2==1)
            out_always =b;
    	else
            out_always =a;
    end
    
    assign out_assign=(sel_b1==1&&sel_b2==1)?b:a;
    
endmodule

结果正确：