verilog刷题笔记007

Fsm hdlc题
状态转换图

module top_module(
    input clk,
    input reset,    // Synchronous reset
    input in,
    output disc,
    output flag,
    output err);

    reg [3:0] state;
    reg [3:0] next_state;
    always@(*)begin
        case(state)
            0:next_state = in?1:0;
            1:next_state = in?2:0;
            2:next_state = in?3:0;
            3:next_state = in?4:0;
            4:next_state = in?5:0;
            5:next_state = in?6:7;
            6:next_state = in?9:8;
            7:next_state = in?1:0;
            8:next_state = in?1:0;
            9:next_state = in?9:0;
        endcase
    end
    
    always@(posedge clk)begin
        if(reset) state <=0;
        else state<=next_state;
    end
    
    assign disc = state==7;
    assign flag = state==8;
    assign err  = state==9;
    
endmodule