fpga图像处理实战-垂直镜像（二）

FPGA实现

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2024/08/20 18:47:24
// Design Name: 
// Module Name: img_vertical_flip
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


module img_vertical_flip(
    input                               clk                        ,
    input                               rst                        ,
    input              [  10: 0]        img_width                  ,
    input              [  10: 0]        img_height                 ,
    input              [  23: 0]        img_data_i                 ,
    input                               valid_i                    ,
    output reg         [  23: 0]        img_data_o                 ,
    output reg                          valid_o                     
);

    parameter                           Depth