vivado U_SET
将具有附加相对位置（RLOC）约束的设计元素分组，这些约束是
分布在整个设计层次结构中，形成一个集合。
U_SET是HDL设计源文件中的一个属性，不会出现在
综合或实施的设计。U_SET在定义相对放置宏时使用，
或者RTL设计中的RPM。有关使用这些属性和定义的更多信息
RPM，请参阅《Vivado设计套件用户指南：使用约束》（UG903）[参考文献19]。
而H_SET或HU_SET用于根据设计定义逻辑元素集
层次结构，您可以手动创建一组用户定义的逻辑元素或U_set，即
不依赖于设计的层次结构。
当RTL源文件中也存在RLOC时，H_SET、HU_SET和U_SET属性
转换为合成网表中单元格的只读RPM属性。HU_SET
在Vivado Design的文本编辑器中的RTL源文件上可以看到U_SET属性
一套。但是，在单元格对象的“属性”窗口中，会显示RPM属性。
重要提示：当附加到分层模块时，U_SET约束会向下传播
通过层次结构，将RLOC约束分配给任何原始符号。
架构支持
所有架构。
适用对象
U_Set约束可用于以下一个或多个设计元素，或
设计元素的类别。请参阅Vivado Design Suite 7系列FPGA和
Zynq-7000 SoC库指南（UG953）[参考25]或UltraScale体系结构库
关于具体设计元素的更多信息，请参阅指南（UG974）[参考26]：
•登记簿
•宏实例
•公羊*
•RAMD*
•漫步*
•DSP48*
Values
•
Syntax
Verilog Syntax
This is a Verilog attribute used in combination with the RLOC property to define the set
content of a hierarchical block that will define an RPM in the synthesized netlist. Place the
Verilog attribute immediately before the instantiation of a logic element.
(* RLOC = "X0Y0", HU_SET = "h0" *) FD sr0 (.C(clk), .D(sr_1n), .Q(sr_0));
Verilog Example
The following Verilog module defines RLOC and U_SET properties for the shift register flops
in the module.
module ffs (
input clk,
input d,
output q
);
wire sr_0, sr_0n;
wire sr_1, sr_1n;
wire sr_2, sr_2n;
wire sr_3, sr_3n;
wire sr_4, sr_4n;
wire sr_5, sr_5n;
wire sr_6, sr_6n;
wire sr_7, sr_7n;
wire inr, inrn, outr;
inv i0 (sr_0, sr_0n);
inv i1 (sr_1, sr_1n);
inv i2 (sr_2, sr_2n);
inv i3 (sr_3, sr_3n);
inv i4 (sr_4, sr_4n);
inv i5 (sr_5, sr_5n);
inv i6 (sr_6, sr_6n);
inv i7 (sr_7, sr_7n);
inv i8 (inr, inrn);
(* RLOC = "X0Y0", U_SET = "Uset0" *) FD sr0 (.C(clk), .D(sr_1n), .Q(sr_0));
(* RLOC = "X0Y0", U_SET = "Uset0" *) FD sr1 (.C(clk), .D(sr_2n), .Q(sr_1));
(* RLOC = "X0Y1", U_SET = "Uset0" *) FD sr2 (.C(clk), .D(sr_3n), .Q(sr_2));
(* RLOC = "X0Y1", U_SET = "Uset0" *) FD sr3 (.C(clk), .D(sr_4n), .Q(sr_3));
(* RLOC = "X0Y0", U_SET = "Uset1" *) FD sr4 (.C(clk), .D(sr_5n), .Q(sr_4));
(* RLOC = "X0Y0", U_SET = "Uset1" *) FD sr5 (.C(clk), .D(sr_6n), .Q(sr_5));
(* RLOC = "X0Y1", U_SET = "Uset1" *) FD sr6 (.C(clk), .D(sr_7n), .Q(sr_6));
(* RLOC = "X0Y1", U_SET = "Uset1" *) FD sr7 (.C(clk), .D(inrn), .Q(sr_7));
(* LOC = "SLICE_X0Y0" *) FD inq (.C(clk), .D(d), .Q(inr));
FD outq (.C(clk), .D(sr_0n), .Q(outr));
assign q = outr;
endmodule // ffs
Unlike the HU_SET property, which applies to the level of hierarchy it is defined in, the
U_SET property transcends hierarchy. In this case, the following top-level module defines
three instances of the ffs module, but results in only two U_SETS being created: Uset_0 and
Uset_1, which contain Flops from all three ffs module instances defined below:
module top (
input clk,
input d,
output q
);
wire c1, c2;
ffs u0 (clk, d, c1);
ffs u1 (clk, c1, c2);
ffs u2 (clk, c2, q);
endmodule // top
VHDL Syntax
Declare the VHDL attribute as follows:
attribute U_SET : string;
Specify the VHDL constraint as follows:
attribute U_SET of {component_name | entity_name | label_name} :
{component|entity|label} is "NAME";
Where:
• { component_name | entity_name | label_name } is a choice of one design element.
• { component | entity | label } is the instance ID of the design element.
• "NAME" is the unique set name to give to the U_SET.
XDC Syntax
The U_SET property can not be defined using XDC constraints. The U_SET property, when
present on logic elements with the RLOC property, defines relatively placed macros (RPMs),
and results in the read-only RPM property in the netlist of synthesized designs.