VCCAUX_IO

VCCAUX_IO指定给定I/O的VCCAUX.IO轨道的工作电压。
DRC可用于确保VCCAUX_IO属性分配正确：
•VCCAUXIOBT（警告）：确保VCCAUX_IO值为NORMAL或HIGH的端口
仅存放在惠普银行。
•VCCAUXIOSTD（警告）：确保VCCAUX_IO值为NORMAL或
HIGH不使用仅在人力资源银行支持的IOSTANDARD。
•VCCAUXIO（错误）：确保VCCAUX_IO值为NORMAL的端口
与VCCAUX_IO值为HIGH的端口约束/放置在同一组中。
架构支持
仅适用于高性能（HP）存储体I/O的7系列FPGA和Zynq-7000 SoC设备。

Syntax

Verilog Syntax

To set this attribute, place the proper Verilog attribute syntax before the top-level output

port declaration.

(* VCCAUXIO = "{DONTCARE|NORMAL|HIGH}" *)

Verilog Syntax Example

// Specifies a “HIGH” voltage for the VCCAUX_IO rail connected to this I/O

(* VCCAUX_IO = "HIGH" *) input ACT3,

VHDL Syntax

To set this attribute, place the proper VHDL attribute syntax before the top-level output

port declaration.

Declare the VHDL attribute as follows:

attribute VCCAUX_IO : string;

Specify the VHDL attribute as follows:

attribute VCCAUX_IO of port_name : signal is value;

Where

• port_name is a top-level port.

VHDL Syntax Example

ACT3 : in std_logic;

attribute VCCAUX_IO : string;

-- Specifies a HIGH voltage for the VCCAUX_IO rail connected to this I/O

attribute VCCAUX_IO of ACT3 : signal is “HIGH”;

XDC Syntax

set_property VCCAUX_IO value [get_ports port_name]

Where

• port_name is a top-level port.

XDC Syntax Example

# Specifies a HIGH voltage for the VCCAUX_IO rail connected to this I/O

set_property VCCAUX_IO HIGH [get_ports ACT3]