RS232

串口程序，可以连续发送和接受

CLK_div是RS232时钟产生模块

另外两个接受和发送模块如下：

  
  

   
   
   
   module
   
    RS_232_r(clk9600,reset,datain,dataout,valid);

   
   input
   
    clk9600,datain,reset;

   
   output
   
    
   
   reg
   
    [
   
   7
   
   :
   
   0
   
   ] dataout;

   
   output
   
    
   
   reg
   
    valid;


   
   reg
   
   [
   
   7
   
   :
   
   0
   
   ] temp;

   
   reg
   
    flag;

   
   reg
   
    [
   
   3
   
   :
   
   0
   
   ] state;


   
   parameter
   
    IDLE
   
   =
   
   4
   
   '
   
   d0,
   
   

   
    S0
   
   =
   
   4
   
   '
   
   d1,
   
   

   
    S1
   
   =
   
   4
   
   '
   
   d2,
   
   

   
    S2
   
   =
   
   4
   
   '
   
   d3,
   
   

   
    S3
   
   =
   
   4
   
   '
   
   d4,
   
   

   
    S4
   
   =
   
   4
   
   '
   
   d5,
   
   

   
    S5
   
   =
   
   4
   
   '
   
   d6,
   
   

   
    S6
   
   =
   
   4
   
   '
   
   d7,
   
   

   
    S7
   
   =
   
   4
   
   '
   
   d8,
   
   

   
    stop
   
   =
   
   4
   
   '
   
   d9;
   
   

   
   always
   
    @(
   
   posedge
   
    clk9600 
   
   or
   
    
   
   negedge
   
    reset)

   
   begin
   
   
 
   
   if
   
   (
   
   !
   
   reset)
 
   
   begin
   
   
 state
   
   <=
   
   IDLE;
 
   
   //
   
   dataout<=8'b11111111;
   
   

   
    flag
   
   <=
   
   1
   
   '
   
   b0;
   
   

   
    valid
   
   <=
   
   1
   
   '
   
   b0;
   
   

   
    
   
   end
   
   
 
   
   else
   
   
 
   
   begin
   
   
 
   
   case
   
   (state)
 IDLE:
 
   
   begin
   
   
 
   
   if
   
   (datain
   
   ==
   
   1
   
   '
   
   b0)
   
   

   
    
   
   begin
   
   
 state
   
   <=
   
   S0;
 flag
   
   <=
   
   1
   
   '
   
   b1;
   
   

   
    valid
   
   <=
   
   1
   
   '
   
   b0;
   
   

   
    
   
   end
   
   
 
   
   else
   
   
 
   
   begin
   
   
 state
   
   <=
   
   IDLE;
 flag
   
   <=
   
   1
   
   '
   
   b0;
   
   

   
    valid
   
   <=
   
   1
   
   '
   
   b0;
   
   

   
    
   
   end
   
   
 
   
   end
   
   
 S0:
 
   
   begin
   
   
 temp[
   
   0
   
   ]
   
   <=
   
   datain;
 state
   
   <=
   
   S1;
 flag
   
   <=
   
   1
   
   '
   
   b1;
   
   

   
    valid
   
   <=
   
   1
   
   '
   
   b0;
   
   

   
    
   
   end
   
   
 S1:
 
   
   begin
   
   
 temp[
   
   1
   
   ]
   
   <=
   
   datain; 
 state
   
   <=
   
   S2;
 flag
   
   <=
   
   1
   
   '
   
   b1;
   
   

   
    valid
   
   <=
   
   1
   
   '
   
   b0;
   
   

   
    
   
   end
   
   
 S2:
 
   
   begin
   
   
 temp[
   
   2
   
   ]
   
   <=
   
   datain; 
 state
   
   <=
   
   S3;
 flag
   
   <=
   
   1
   
   '
   
   b1;
   
   

   
    valid
   
   <=
   
   1
   
   '
   
   b0;
   
   

   
    
   
   end
   
   
 S3:
 
   
   begin
   
   
 temp[
   
   3
   
   ]
   
   <=
   
   datain; 
 state
   
   <=
   
   S4;
 flag
   
   <=
   
   1
   
   '
   
   b1;
   
   

   
    valid
   
   <=
   
   1
   
   '
   
   b0;
   
   

   
    
   
   end
   
    
 S4:
 
   
   begin
   
   
 temp[
   
   4
   
   ]
   
   <=
   
   datain; 
 state
   
   <=
   
   S5;
 flag
   
   <=
   
   1
   
   '
   
   b1;
   
   

   
    valid
   
   <=
   
   1
   
   '
   
   b0;
   
   

   
    
   
   end
   
   
 S5:
 
   
   begin
   
   
 temp[
   
   5
   
   ]
   
   <=
   
   datain; 
 state
   
   <=
   
   S6;
 flag
   
   <=
   
   1
   
   '
   
   b1;
   
   

   
    valid
   
   <=
   
   1
   
   '
   
   b0;
   
   

   
    
   
   end
   
   
 S6:
 
   
   begin
   
   
 temp[
   
   6
   
   ]
   
   <=
   
   datain; 
 state
   
   <=
   
   S7;
 flag
   
   <=
   
   1
   
   '
   
   b1;
   
   

   
    valid
   
   <=
   
   1
   
   '
   
   b0;
   
   

   
    
   
   end
   
   
 S7:
 
   
   begin
   
   
 temp[
   
   7
   
   ]
   
   <=
   
   datain; 
 state
   
   <=
   
   stop;
 flag
   
   <=
   
   1
   
   '
   
   b0;
   
   

   
    valid
   
   <=
   
   1
   
   '
   
   b1;
   
   

   
    
   
   end
   
   
 stop:
 
   
   begin
   
   
 state
   
   <=
   
   IDLE;
 dataout
   
   <=
   
   temp;
 flag
   
   <=
   
   1
   
   '
   
   b0;
   
   

   
    valid
   
   <=
   
   1
   
   '
   
   b0;
   
   

   
    
   
   end
   
    
 
   
   endcase
   
   
 
   
   end
   
   

   
   end
   
   

   
   endmodule
   
    
  
  

发送模块：

  
  

   
   
   
   module
   
    rs232_tx
(
 
   
   input
   
    clk,
 
   
   input
   
    rst_n,
 
   
   input
   
    flag,
 
   
   input
   
    [
   
   7
   
   :
   
   0
   
   ] rx,
 
   
   output
   
    
   
   reg
   
    dataout
);


   
   reg
   
   [
   
   9
   
   :
   
   0
   
   ] temp;

   
   integer
   
    index;

   
   reg
   
    valid;

   
   always
   
    @ (
   
   posedge
   
    clk 
   
   or
   
    
   
   negedge
   
    rst_n)

   
   begin
   
   
 
   
   if
   
   (
   
   !
   
   rst_n)
 
   
   begin
   
   
 dataout 
   
   <=
   
    
   
   1
   
   '
   
   b1;
   
   

   
    valid 
   
   <=
   
    
   
   1
   
   '
   
   b0;
   
   

   
    
   
   //
   
   temp <= 10'b1111111111;
   
   

   
    
   
   end
   
   
 
   
   else
   
   
 
   
   begin
   
   
 
   
   if
   
   (flag)
 
   
   begin
   
   
 temp 
   
   <=
   
    {
   
   1
   
   '
   
   b1,rx[7:0],1
   
   '
   
   b0};
 valid 
   
   <=
   
   1
   
   '
   
   b1;
   
   

   
    index 
   
   <=
   
    
   
   0
   
   ;
 dataout 
   
   <=
   
   1
   
   '
   
   b1;
   
   

   
    
   
   end
   
   
 
   
   else
   
   
 
   
   if
   
   (valid
   
   ==
   
   1
   
   '
   
   b1)
   
   

   
    
   
   begin
   
   
 dataout 
   
   <=
   
    temp[index];
 
   
   if
   
   (index
   
   ==
   
   9
   
   )
 valid 
   
   <=
   
   1
   
   '
   
   b0;
   
   

   
    
   
   else
   
   
 valid 
   
   <=
   
   1
   
   '
   
   b1;
   
   

   
    index 
   
   <=
   
    index 
   
   +
   
   1
   
   '
   
   b1;
   
   

   
    
   
   end
   
   
 
   
   else
   
   
 dataout 
   
   <=
   
   1
   
   '
   
   b1;
   
   

   
    
   
   end
   
   

   
   end
   
    

   
   endmodule
   
    
  
  

时序图：