VPFE寄存器描述

寄存器描述:
一.CCDC
1.Synchronization Enable Register (SYNCEN)
0:VDHDEN
1:WEN
2.MODESET
15:FLDSTAT 0:ODD FIELD 1:EVEN FIELD
14:LPF 3-tap Low-Pass (anti-aliasing) filter for ccd data 0:off 1:on
13-12:INPMOD INPUT MODE 0:CCD RAW DATA 1:YCBCR 16BIT 2:YCBCR 8BIT
11:PACK8 0:NORMAL 16BIT TO SDRAM 1:PACK8 BIT TO SDRAM
10-8:DATASFT 0:NO SHIFT 1-6:SHIFT 1-6BIT
7:FLDMODE 0:NON-INTERFACED 1：INTERFACED （若EXWEN =1，则需为0）
6:DATAPOL 0:NORMAL 1:ONE'S CONPLEMENT
5:EXWEN 0:不用外部WEN 1:用外部VD/HD作为写SDRAM的信号
4:FLDPOL 0:POSITIVE 1:NEGATIVE
3:HDPOL 意思同上
2:VDPOL 意思同上
0:VDHDOUT 0:VD,HD INPUT 1:VD,HD OUTPUT
3. Horizontal Size Register (HSIZE)
12:ADR_UPDT SDRAM 地址更新方式0:自动增加 1:自动减少
11-0:LNOFST SDRAM中行尺寸,32BYTE为单位即16或32PIXELS
4.SDRAM Line Offset Register (SDOFST)
14：FIINV 0：NON INVERSE 1：INVERSE
13-12：FOFST Line offset value of odd field (FID = 1) 0-3：+1 - +4
11-9：LOFST0 Line offset values of even line and even field (FID = 0) 0-7：+1 - -4
8-6：LOFST1 Line offset values of odd line and even field (FID = 0) 同上
5-3：LOFST2 Line offset values of even line and odd field (FID = 1) 同上
2-0：LOFST3 Line offset values of odd line and odd field (FID = 1)同上
5.SDRAM Address - High Register (STADRH)
6.SDRAM Address - LOW Register (STADRL)
7.CCD Color Pattern Register (COLPTN)
8. CCD Gain Adjustment - R/Ye Register (RYEGAIN)
CCD Gain Adjustment - Gr/Cy Register (GRCYGAIN)
CCD Gain Adjustment - Gb/G Register (GBGGAIN)
CCD Gain Adjustment - B/Mg Register (BMGGAIN)
CCD Offset Adjustment Register (OFFSET)
9.Output Clipping Value Register (OUTCLIP)
10.VD Interrupt #0 Register (VDINT0) 中断设定行数
11. VD Interrupt #1 Register (VDINT1)
12. Gamma Correction Settings Register (GAMMAWD)
11-10:MFIL1 Median filter mode for IPIPE 0:no filer 1:average filer 2:median filer
9-8: MFIL1 Median Filter for SDRAM capture.值同上
5：CFAP CFA Pattern. 0：Mosaic 1：Stripe
4-2：GWDI Gamma Width Input (For A-LAW table & H3A port)
0：BITS 13-4 1：12-3 2：11-2 3：10-1 4：9-0
0：CCDTBL Apply Gamma (A-LAW) to CCDC data saved to SDRAM 0：DISABLE 1：ENABLE
13. REC656 Control Register (REC656IF)
1: ECCFVH FVH error correction enable 0:DISABLE 1:ENABLE
0: R656ON REC656 interface enable 0:DISABLE 1:ENABLE
14. CCD Configuration Register (CCDCFG)
15:VDLC Enable synchronizing function regs on VSYNC. 0:Latched on VSYNC. 1:NO LATCHED
13:MSBINVI MSB of Chroma input signal stored to SDRAM inverted.0:NORMAL 1:MSB INVERTED
12:BSWD Byte swap data stored to SDRAM. 0:NORMAL 1:BYTE SWAP
11:Y8POS Location of Y signal when YCbCr 8bit data is input.0:EVEN PIXEL 1:ODD PIXEL
10:EXTRG External trigger.0:DIABLE 1:ENABLE
9:TRGSEL Signal that initializes SDRAM address when EXTRG = 1.
0: WEN bit (SYNCEN register).1:FID input port.
8:WENLOG Specifies CCD valid area.
0:Internal valid and WEN signals are ANDed logically.
1:Internal valid and WEN signals are ORed logically.
6:FIDMD Setting of FID detection function.
0:FID signal is latched at the VSYNC 1: FID signal is not latched.
5:BW656 The data width in REC656 input mode. 0:8BIT 1:10BIT
4:YCINSWP Y input (YIN[7:0]) and C input (CIN[7:0]) are swapped.
0:(NO_YCIN_SWAP) YIN[7:0] = Y signal / CIN[7:0] = C signal.
1:(YCIN_SWAP) YIN[7:0] = C signal / CIN[7:0] = Y signal.
15. Start Pixel Horizontal Register (FMTSPH) 针对CFA,即CMYG TO RGBG转换
16. Number Of Pixels Register (FMTLNH) 同上
17. Start Line Vertical Register (FMTSLV) 同上
18. Number of Lines Register (FMTLNV) 同上
19. Lens Shading Correction Configuration 1 Register (LSCCFG1) 同上
20. Lens Shading Correction Configuration 2 Register (LSCCFG2)
21. Lens Shading Correction - Center Position (H0) Register (LSCH0)
22. Lens Shading Correction - Center Position (V0) Register (LSCV0)
23. Lens Shading Correction - Horizontal Coefficients Register (LSCKH)
24. Lens Shading Correction - Vertical Coefficients Register (LSCKV)
25. Lens Shading Correction - Memory Control Register (LSCMEMCTL)
26. Lens Shading Correction - Memory Read Data Register (LSCMEMQ)
27. Defect Correction - Control Register (DFCCTL)
28. Defect Correction - Vertical Saturation Level Register (DFCVSAT)
29. Defect Correction - Memory Control Register (DFCMEMCTL)
30. Defect Correction - Set V Position Register (DFCMEM0)
31. Defect Correction - Set H Position Register (DFCMEM1)
32. Defect Correction - Set SUB1 Register (DFCMEM2)
33. Defect Correction - Set SUB2 Register (DFCMEM3)
34. Defect Correction - Set SUB3 Register (DFCMEM4)
35. Color Space Converter Enable Register (CSCCTL)
36. Color Space Converter - Coefficients #0 Register (CSCM0)-(CSCM7)
37. Data Offset Register (DATAOFST)
15-8 VOFST V direction data offset for defect correction and lens shading correction. Range: 0-255.
7-0 HOFST H direction data offset for defect correction and lens shading Correction. Range: 0-255.
二.IPIPEIF
1. IPIPE I/F Enable Register (ENABLE)
0:ENABLE SDRAM BUFFE读开始信号及产生SYNC信号 ,只有在INPSRC (CFG[3:2]) = 1, 2 or 3.下有用(CFG)
13-11:DATASFT SDRAM Read Data Shift (0_6) 当INPSRC = 1 or 2.有效
0 Output data (13:0) = read data(15:2)
1 Output data (13:0) = read data(14:1)
2 Output data (13:0) = read data(13:0)(
3 Output data (13:0) = read data(12:0) & "0"
4 Output data (13:0) = read data11:0) & "00"
5 Output data (13:0) = read data(10:0) & "000"
6 Output data (13:0) = read data(9:0) & "0000"
2. IPIPE I/F Configuration Register
10: CLKSEL
IPIPEIF & IPIPE Clock Select
This register is available when INPSRC = 1 or 3. Should code "0" when INPSRC = 0 or 2.
0 Pixel clock (PCLK)
1 Divided SDRAM clock as per CLKDIV
9: IALAW Inverse A-law Conversion
Applies inverse A-law (8bit to 10bit) conversion to the SDRAM data.
This register is available when= INPSRC 1 or 2.
0 Inverse alaw off
1 Inverse alaw on
8: PACK8IN 8-Bit Packed Mode INPSRC 1 or 2.有效
0 (NORMAL_16_BITS_PIXEL) 16 bits / pixel
1 (PACK_8_BITS_PIXEL) 8 bits / pixel
7 :AVGFILT Averaging Filter
It applies (1,2,1) filter for the RGB/YCbCr data.
0 Off
1 On
6-4: CLKDIV Clock Selection when Offline Mode (SDRAM Input? Mode)
IPIPEIF/IPIPE clock frequency = CLKDIV x VPSSCLK clock frequency(CLKSEL=1)
0-4:1/2-1/6 5:1/8 6:1/16 7:1/32
3-2: INPSRC CCD/YCbCr Data Port Selection
0 From CCD Controller
1 From SDRAM (raw data)
2 From CCD Controller & SDRAM (Darkframe)
3 From SDRAM (YCbCr data)
1: DECM Pixel Decimation
Decimation rate defined by RSZ register
0 No decimation
1 Decimate
0: ONESHOT One Shot Mode
This register is available when INPSRC = 1 or 3.
0 Continuous mode
1 One shot mode
3. IPIPE I/F Interval of HD / Start pixel in HD Register (PPLN)
4. IPIPE I/F Number of valid pixels per line Register (HNUM)
5. IPIPE I/F Number of Valid Lines per Frame Register (VNUM)
6. IPIPE I/F Memory Address (Upper) Register (ADDRU)
7. IPIPE I/F Memory Address (Lower) Register (ADDRL)
8. IPIPE I/F Address Offset of Each Line Register (ADOFS)
9. IPIPE I/F Horizontal Resizing Parameter Register (RSZ)(当水平像素大于1344时用到）
6-0 RSZ 10h-70h The Horizontal Resizing Parameter 水平RESIZE参数，16到112，以16/RSZ计算
10. IPIPE I/F Gain Parameter Register (GAIN)
三.IPIPE
1. IPIPE Enable Register (IPIPE_EN)
0:EN 在ONE-SHOT模式下,处理完一FRAME后EN自动清0
2. One Shot Mode Register (IPIPE_MODE)
1: WRT CAM_WEN mode selection.WRT=0则不管CAM_WEN,处理每一FRAME;WRT=1,则当CAM_WEN有效时处理(当时序有IPIPEIF产生时,应设为0)
0 ONESHOT One shot mode.
3. Input/Output Data Paths Register (IPIPE_DPATHS)
2 BYPASS Enable RAW-Bypass mode through IPIPE. 当设定时输入影像宽度可以达到4096PIXEL(只当FMT=1有效)
0-1 FMT Data Path through IPIPE.
0 (RAW2YUV) Bayer input, YCbCr (or RGB) output.
1 (RAW2RAW) Bayer input, Bayer output.
2 (RAW2BOX) Bayer input, Boxcar output.
3 (YUV2YUV) YCbCr (16bit) input, YCbCr (or RGB) output
4. Color Pattern Register (IPIPE_COLPAT)
5. Vertical Start Position Register (IPIPE_VST)
6. Vertical Processing Size Register (IPIPE_VSZ)
7. Horizontal Start Position Register (IPIPE_HST)
8. Horizontal Processing Size Register (IPIPE_HSZ)
9. ARM Gated Clock Control Register (GCL_ARM)
0 REG IPIPE MMR clock enable.
The on/off selection of the MMR interface clock which is used for ARM register accesses.
0 Off
1 On
10. CCD Gated Clock Control Register (GCL_CCD)
2 G2 IPIPE G2 clock enable.
The on/off selection of the clock which is used for the IPIPE processing of "CFA" to "422", "Histogram".
0 Off
1 On
1 G1 IPIPE G1 clock enable.
The on/off selection of the clock which is used for the IPIPE processing of "Defect Correction" to "WhiteBalance".
0 Off
1 On
0 G0 IPIPE G0 clock enable.
The on/off selection of the clock which is used for the IPIPE processing of "Boxcar".
0 Off
1 On
11. SDR Gated Clock Control Register (GCL_SDR)( RESIZER模块时钟能动，当为0时在RESIZER BYPASS模式）
0 RSZ IPIPE RSZ clock enable.
The on/off selection of the clock which is used for "Resize". The resizer operates in bypass mode when
this is off.
0 Off
1 On
12. Internal Table Selection Register (RAM_MODE)
13. Address Register (RAM_ADR)
14. Write Data Register (RAM_WDT)
15. Read Data Register (RAM_RDT)
16. Interrupt Enable Register (IRQ_EN)
17. Interval of IRQ-2 Register (IRQ_RZA)
12-0 VAL 0-1FFFh Interval of IRQ_2. Interrupt signal at every (VAL + 1) lines of Resize and RGB output.
18. Interval of IRQ-3 Register (IRQ_RZB)
12-0 VAL 0-1FFFh Interval of IRQ_3. Interrupt signal at every (VAL + 1) lines of Resize and RGB output
19. Defect Correction Enable Register (DFC_EN)
20. Copy Method Selection (from Top or from Bottom) Register (DFC_SEL)
21. Start Address in LUT Register (DFC_ADR)
22. Number of Available Entries in LUT Register (DFC_SIZ)
23. 2D Noise Filter Enable Register (D2F_EN)
24. Noise Filter Configuration Register (D2F_CFG)
25. Noise Filter LUT Values (Threshold) Register (D2F_THR[32])
26. Noise Filter LUT Values (Intensity) Register (D2F_STR[32])
27. PreFilter Enable Register (PRE_EN)
28. PreFilter Type Register (PRE_TYP)
29. Shift Value of Adaptive Gain Register (PRE_SHF)
30. Constant Gain or Adaptive Gain Slope Register (PRE_GAIN)
31. Threshold G Register (PRE_THR_G)
32. Threshold B Register (PRE_THR_B)
33. Threshold 1 Register (PRE_THR_1)
34. Digital Gain Register (WB2_DGN)
35. White Balance Gain Register (WB2_WG_R),(WB2_WG_GR),(WB2_WG_GB)(WB2 _WG_B)
36. Matrix Coefficient RR Register (RGB_MUL_RR),RGB_MUL_GR,RGB_MUL_BR),(RGB_MUL_RG)
37. Matrix Coefficient GG Register (RGB_MUL_GG),(RGB_MUL_BG),(RGB_MUL_RB),(RGB_MUL_GB),(RGB_MUL_BB)
38. R Output Offset Register (RGB_OFT_OR),(RGB_OFT_OG),(RGB_OFT_OB)
39. Gamma Correction Configuration Register (GMM_CFG)
40. Luminance Adjustment (Contrast and Brightness) Register (YCC_ADJ)
41. Matrix Coefficient RY Register (YCC_MUL_RY),(YCC_MUL_GY),(YCC_MUL_BY),(YCC_MUL_RCB),(YCC_MUL_GCB),(YCC_MUL_BCB),(YCC_MUL_RCR),(YCC_MUL_GCR),(YCC_MUL_BCR)
42. Y Output Offset Register (YCC_OFT_Y)
43. Cb Output Offset Register (YCC_OFT_CB)
44. Cr Output Offset Register (YCC_OFT_CR)
45. Saturation (Luminance Minimum) Register (YCC_Y_MIN)
46. Saturation (Luminance Maximum) Register (YCC_Y_MAX)
47. Saturation (Chrominance Minimum) Register (YCC_C_MIN)
48. Saturation (Chrominance Maximum) Register (YCC_C_MAX)
49. Chrominance Position (for 422 Down Sampler) Register (YCC_PHS)(当输入为YCBCR时）
50. Edge Enhancer Enable Register (YEE_EN)
51. MedianNR Enable Register (YEE_EMF)
52. HPF Shift Length Register (YEE_SHF)
53. HPF Coefficient 00 Register (YEE_MUL_00，01，02，10，11，12，20，21，22)
54. Fault Color Suppression Enable Register (FCS_EN)
55. Type selection of HPF Register (FCS_TYP)
56. Down Shift Size (HPF) Register (FCS_SHF_Y)
57. Down Shift Size (GAIN) Register (FCS_SHF_C)
58. Threshold Register (FCS_THR)
59. Intensity Register (FCS_SGN)
60. Processing Mode Register (RSZ_SEQ)
4 CRV Chroma sampling point change.
0 Chroma sampling point is not changed.
1 Chroma sampling point is changed from odd-numbered pixels to even-number pixels. The pixel the leftend is removed and the pixel at the right end is duplicated.
3 VRV Vertical reversal of output image.
0 Processed lines are output in the order of input (normal operation) in vertical direction.
1 The order of output data is flipped top to bottom.
2 HRV Horizontal reversal of output image.
0 Processed pixels are output in the order of input (normal operation) in horizontal direction.
1 The order of output data is flipped left to right.
1 TMM Terminal condition of vertical processing.
0 Output line number confined mode (normal mode). The module continues output of resized image untilthe number of output lines reaches the value set by RZA_O_VSZ and RZB_O_VSZ.
1 Input line number confined mode. The modules continues output of resized image until the inputnumber of input lines reads the value set by RZA_I_VSZ and RZB_I_VSZ. The numbers of output linesare output to RZA_V_SIZ_O and RZB_V_SIZ_O.
0 SEQ Operation mode of vertical processing.
0 Normal mode. The module clears register values and internal buffer values at VSYNC.
1 Continuous mode. Resizer holds values from the previous operation. This mode may only be used incombination with input line number confined mode (TMM=1).
61. Vertical Anti aliasing Filter Register (RSZ_AAL)
62. Resizer Enable Register (RSZ_EN)
63. One Shot Mode Register (RSZ_MODE)
0 OST One shot mode enable.
0 Continuous mode.
1 One shot mode.
64. Vertical Start Position of the Input Register (RSZ_I_VST)
11-0 VAL 0-FFFh Vertical start position of image processing.
After IPIPE_VST, the VAL line is processed as the first line in each image.(在IPIPE_VST之后计算)
65. Vertical Size of the Input Register (RSZ_I_VSZ)
11-0 VAL 0-FFFh Number of input lines. This value is used only in input line confined mode.(RSZ_SEQ[TMM] at 0108h).
The number of input lines is (VAL + 1).
66. Horizontal Start Position of the Input Register (RSZ_I_HST)
11-0 VAL 0-FFFh Horizontal start position of image processing.
(RSZ_I_HST[0] is held low so this value must be even). After IPIPE_HST, the VAL pixel is
processed as the first pixel.
67. Vertical Size of the Output Register (RSZ_O_VSZ)
11-0 VAL 0-FFFh Vertical size of the output image.
The number of output lines is (VAL + 1). (RSZ_O_VSZ[0] is held high so this value must be odd).
68. Horizontal Start Position of the Output Register (RSZ_O_HST)
11-0 VAL 0-FFFh Horizontal position of the first pixel to be output in processed image.
The first VAL pixels of the resized area in each line are discarded, and the next pixel becomes the first
to be output. (RSZ_O_HST[0] is held low so this value must be even).
69. Horizontal Size of the Output Register (RSZ_O_HSZ)
11-0 VAL 0-FFFh Horizontal size of output image. The number of pixel in each line is (VAL + 1).
RSZ[0]:Value must be lower than 1344 except in RAW passthu mode.
RSZ[1]:Value must be lower than 640. (RSZ_O_HSZ[0] is held high so this value must be odd).
70. Initial Phase of Vertical Resizing Process Register (RSZ_V_PHS)
13-0 VAL 0-3FFFh Initial value for the phase value in vertical resizing process. (Should be set to zero except in Frame
Division Mode-H). Valid range: 0-8191.
71. Phase of Last Value in Previous Resize Process Register (RSZ_V_PHS_O)
13-0 VAL 0-3FFFh Phase value of the last line in the previous resizing process. This value is only valid in input line
number confined mode ((RSZ_SEQ[TMM] at 0x0108).
72. Vertical Resize Parameter Register (RSZ_V_DIF)
13-0 VAL 0-3FFFh Vertical resize parameter. The actual resizing ratio is 256/VAL.
73. Actual Number of Output Lines Register (RSZ_V_SIZ_O)
12-0 VAL 0-1FFFh Number of actually produced lines in the previous resizing process
74. Initial Phase of Horizontal Resizing Process Register (RSZ_H_PHS)