检测恒定电平模块

  
    

   
     
 1 
   
     ---------------------------------------------------------------------------------
   
     

   
      2 
   
     
   
     --
   
      Created by : Vorx Ltd.com

   
      3 
   
     
   
     --
   
      Filename : only_value.vhd

   
      4 
   
     
   
     --
   
      Author : ChenYong

   
      5 
   
     
   
     --
   
      Created On : 
   
     2011
   
     -
   
     05
   
     -
   
     10
   
      
   
     15
   
     :
   
     10
   
     

   
      6 
   
     
   
     --
   
      Last Modified : 
   
     2011
   
     -
   
     05
   
     -
   
     10
   
      
   
     15
   
     :
   
     31
   
     

   
      7 
   
     
   
     --
   
      Version : v1.
   
     0
   
     

   
      8 
   
     
   
     --
   
      Description : 检测输入数据是否为恒值，如果为恒值则输出1，如果有变化则输出0
  
    
  
    

   
      9 
   
     
   
     --
   
      主要思想还是数位延迟异或。

   
     10 
   
     
   
     --
   
      

   
     11 
   
     
   
     ---------------------------------------------------------------------------------
   
     

   
     12 
   
     

   
     13 
   
     
   
     library
   
      ieee;

   
     14 
   
     
   
     use
   
      ieee.std_logic_1164.
   
     all
   
     ;

   
     15 
   
     
   
     use
   
      ieee.std_logic_arith.
   
     all
   
     ;

   
     16 
   
     
   
     use
   
      ieee.std_logic_unsigned.
   
     all
   
     ;

   
     17 
   
     

   
     18 
   
     
   
     entity
   
      det_constant 
   
     is
   
     

   
     19 
   
      
   
     port
   
     (

   
     20 
   
      clk : 
   
     in
   
      
   
     std_logic
   
     ;

   
     21 
   
      rst : 
   
     in
   
      
   
     std_logic
   
     ;

   
     22 
   
      data_in : 
   
     in
   
      
   
     std_logic_vector
   
     (
   
     3
   
      
   
     downto
   
      
   
     0
   
     );

   
     23 
   
      not_change : 
   
     out
   
      
   
     std_logic
   
     

   
     24 
   
      );

   
     25 
   
     
   
     end
   
      det_constant;

   
     26 
   
     

   
     27 
   
     
   
     architecture
   
      arc 
   
     of
   
      det_constant 
   
     is
   
     

   
     28 
   
     

   
     29 
   
      
   
     signal
   
      data_in_dly0 : 
   
     std_logic_vector
   
     (
   
     3
   
      
   
     downto
   
      
   
     0
   
     );

   
     30 
   
      
   
     signal
   
      data_in_dly1 : 
   
     std_logic_vector
   
     (
   
     3
   
      
   
     downto
   
      
   
     0
   
     );

   
     31 
   
      
   
     signal
   
      cnt_change : 
   
     std_logic_vector
   
     (
   
     20
   
      
   
     downto
   
      
   
     0
   
     );

   
     32 
   
      
   
     signal
   
      cnt_clr : 
   
     std_logic
   
     ;

   
     33 
   
     

   
     34 
   
     
   
     begin
   
     

   
     35 
   
     

   
     36 
   
      
   
     process
   
     (clk,rst)

   
     37 
   
      
   
     begin
   
     

   
     38 
   
      
   
     if
   
      rst 
   
     =
   
      
   
     '
   
     1
   
     '
   
      
   
     then
   
      

   
     39 
   
      data_in_dly0 
   
     <=
   
      (
   
     others
   
     =>
   
     '
   
     0
   
     '
   
     );

   
     40 
   
      data_in_dly1 
   
     <=
   
      (
   
     others
   
     =>
   
     '
   
     0
   
     '
   
     );

   
     41 
   
      elsif 
   
     rising_edge
   
     (clk) 
   
     then
   
      

   
     42 
   
      data_in_dly0 
   
     <=
   
      data_in;

   
     43 
   
      data_in_dly1 
   
     <=
   
      data_in_dly0;

   
     44 
   
      
   
     end
   
      
   
     if
   
     ; 

   
     45 
   
      
   
     end
   
      
   
     process
   
     ;

   
     46 
   
     

   
     47 
   
      cnt_clr 
   
     <=
   
      (data_in_dly0(
   
     0
   
     ) 
   
     xor
   
      data_in_dly1(
   
     0
   
     )) 
   
     or
   
      (data_in_dly0(
   
     1
   
     ) 
   
     xor
   
      data_in_dly1(
   
     1
   
     ))

   
     48 
   
      
   
     or
   
      (data_in_dly0(
   
     2
   
     ) 
   
     xor
   
      data_in_dly1(
   
     2
   
     )) 
   
     or
   
      (data_in_dly0(
   
     3
   
     ) 
   
     xor
   
      data_in_dly1(
   
     3
   
     ));

   
     49 
   
     

   
     50 
   
      
   
     process
   
     (clk,rst)

   
     51 
   
      
   
     begin
   
     

   
     52 
   
      
   
     if
   
      rst 
   
     =
   
      
   
     '
   
     1
   
     '
   
      
   
     then
   
      

   
     53 
   
      cnt_change 
   
     <=
   
      (
   
     others
   
     =>
   
     '
   
     0
   
     '
   
     );

   
     54 
   
      elsif 
   
     rising_edge
   
     (clk) 
   
     then
   
      

   
     55 
   
      
   
     if
   
      cnt_clr 
   
     =
   
      
   
     '
   
     1
   
     '
   
      
   
     then
   
      

   
     56 
   
      cnt_change 
   
     <=
   
      (
   
     others
   
     =>
   
     '
   
     0
   
     '
   
     );

   
     57 
   
      elsif cnt_change(
   
     20
   
     ) 
   
     =
   
      
   
     '
   
     0
   
     '
   
      
   
     then
   
      

   
     58 
   
      cnt_change 
   
     <=
   
      cnt_change 
   
     +
   
      
   
     1
   
     ;

   
     59 
   
      
   
     end
   
      
   
     if
   
     ;

   
     60 
   
      
   
     end
   
      
   
     if
   
     ; 

   
     61 
   
      
   
     end
   
      
   
     process
   
     ;

   
     62 
   
     

   
     63 
   
      not_change 
   
     <=
   
      cnt_change(
   
     20
   
     );

   
     64 
   
     

   
     65 
   
     
   
     end
   
      arc;
  
    

  
    

   
      1 
   
     //
   
     -------------------------------------------------------------------------------

   
      2 
   
     
   
     //
   
      Created by : Vorx Ltd.com

   
      3 
   
     
   
     //
   
      Filename : det_constant.v

   
      4 
   
     
   
     //
   
      Author : ChenYong

   
      5 
   
     
   
     //
   
      Created On : 2011-05-10 15:32

   
      6 
   
     
   
     //
   
      Last Modified : 2011-05-10 15:39

   
      7 
   
     
   
     //
   
      Version : v1.0

   
      8 
   
     
   
     //
   
      Description : 

   
      9 
   
     
   
     //
   
      

   
     10 
   
     
   
     //
   
      

   
     11 
   
     
   
     //
   
     -------------------------------------------------------------------------------
   
     

   
     12 
   
     
   
     

   
     13 
   
     `timescale 1ns 
   
     /
   
      1ps

   
     14 
   
     

   
     15 
   
     
   
     module
   
      det_constant

   
     16 
   
     (

   
     17 
   
      clk,

   
     18 
   
      rst,

   
     19 
   
      data_in,

   
     20 
   
      not_change

   
     21 
   
     );

   
     22 
   
     

   
     23 
   
     
   
     input
   
      clk;

   
     24 
   
     
   
     input
   
      rst;

   
     25 
   
     
   
     input
   
      [
   
     3
   
     :
   
     0
   
     ] data_in;

   
     26 
   
     
   
     output
   
      not_change;

   
     27 
   
     

   
     28 
   
     
   
     reg
   
      [
   
     3
   
     :
   
     0
   
     ] data_in_dly0;

   
     29 
   
     
   
     reg
   
      [
   
     3
   
     :
   
     0
   
     ] data_in_dly1;

   
     30 
   
     
   
     wire
   
      cnt_clr;

   
     31 
   
     
   
     reg
   
      [
   
     20
   
     :
   
     0
   
     ] cnt_change;

   
     32 
   
     

   
     33 
   
     
   
     assign
   
      cnt_clr 
   
     =
   
      
   
     |
   
     (data_in_dly0
   
     ^
   
     data_in_dly1);

   
     34 
   
     
   
     assign
   
      not_change 
   
     =
   
      cnt_change[
   
     20
   
     ];

   
     35 
   
     

   
     36 
   
     
   
     always
   
      @ (
   
     posedge
   
      clk 
   
     or
   
      
   
     posedge
   
      rst) 
   
     begin
   
      

   
     37 
   
      
   
     if
   
      (rst) 
   
     begin
   
      

   
     38 
   
      data_in_dly0 
   
     <=
   
      
   
     4
   
     '
   
     b0;
   
     

   
     39 
   
     
   
      data_in_dly1 
   
     <=
   
      
   
     4
   
     '
   
     b0;
   
     

   
     40 
   
     
   
      
   
     end
   
     

   
     41 
   
      
   
     else
   
      
   
     begin
   
     

   
     42 
   
      data_in_dly0 
   
     <=
   
      data_in;

   
     43 
   
      data_in_dly1 
   
     <=
   
      data_in_dly0;

   
     44 
   
      
   
     end
   
     

   
     45 
   
     
   
     end
   
     

   
     46 
   
     

   
     47 
   
     
   
     always
   
      @ (
   
     posedge
   
      clk 
   
     or
   
      
   
     posedge
   
      rst) 
   
     begin
   
      

   
     48 
   
      
   
     if
   
      (rst) 
   
     begin
   
      

   
     49 
   
      cnt_change 
   
     <=
   
      
   
     21
   
     '
   
     b0;
   
     

   
     50 
   
     
   
      
   
     end
   
     

   
     51 
   
      
   
     else
   
      
   
     begin
   
     

   
     52 
   
      
   
     if
   
      (cnt_clr) 
   
     begin
   
      

   
     53 
   
      cnt_change 
   
     <=
   
      
   
     21
   
     '
   
     b0;
   
     

   
     54 
   
     
   
      
   
     end
   
     

   
     55 
   
      
   
     else
   
      
   
     if
   
      (
   
     ~
   
     cnt_change[
   
     20
   
     ]) 
   
     begin
   
      

   
     56 
   
      cnt_change 
   
     <=
   
      cnt_change 
   
     +
   
      
   
     1
   
     ; 

   
     57 
   
      
   
     end
   
      

   
     58 
   
      
   
     end
   
     

   
     59 
   
     
   
     end
   
     

   
     60 
   
     

   
     61 
   
     

   
     62 
   
     

   
     63 
   
     
   
     endmodule
  
    

verilog明显比vhdl简化很多。