Synthesis Script Templet

#*******************************************************************************************
# File name:   syn_script_templet.tcl
# Author:        WangQiang
# Description: This file is just only a templet for synthesis, including basic synthesis flow.
#                     Users can make it as reference design.               
#*******************************************************************************************

remove_design -all

#****************************
# read design to DC memory, Assuming there are four modules
#****************************

read -f verilog ../design/mod.v
read -f verilog ../design/mod1.v
read -f verilog ../design/mod2.v
read -f verilog ../design/mod3.v

# or read like this

set all_modules {mod mod1 \
          mod2 mod3 \
}

foreach (current_module, all_modules)
{
set design_path {../}
}

#******************************/
# Set_dont_touch Attribute on cell, net, reference or design
# Set_dont_touch_network Attribute on clock, pin, ports
#******************************/

set_dont_touch_network find(port,"CLK")

set_dont_touch [get_cells {xxxx/xxxx/aaa}]
set_dont_touch [get_nets {bbbb}]
set_dont_touch [get_designs {ssss}]

#******************************/
# create clock info
#******************************/
create_clock -name clk -period 2.56 -waveform {0 1.28} [get_pins ,{s_x/I_PMA/I_PMA7/RXBCLK}]
create_generated_clock -name clk_125 -source A_x/clk -edges {1 3 5} [get_pins {p_x/clk_125}]

set_clock_uncertainty -setup 0.2 clk
set_clock_uncertainty -hold 0.02 clk
set_clock_uncertainty -setup 0.2 clk_125
set_clock_uncertainty -hold 0.02 clk_125

#******************************/
# exceptions
#******************************/

set_false_path -from clk_m    -to clk_125
set_max_delay 8 -from [get_pins {a_x/A}] -to [get_pins {P_x/x_x/d}]
current_design mcucore
set_multicycle_path 3 -through alu_x/mulb_x/*

#******************************/
# Set Disable Timing    
#******************************/
set_disable_timing -from CLKA -to CLKB synopsys_mem/TP8X16C1
set_disable_timing -from CLKB -to CLKA synopsys_mem/TP8X16C1

#*******************************/
# Report Clock Related Information
#*******************************/
report_clock -attributes > ./design/report_clock.rep
report_clock -skew >> ./design/report_clock.rep
report_design > ./design/report_design.rep
report_port -verbose > ./design/report_port.rep

#*******************************/
# Set Wire_load_model
#*******************************/
link
set_wire_load_model -name KME_DEFAULT -library j1oa
set_wire_load_mode enclosed

#*******************************/
# Load & Input_transition Related Information
#*******************************/
set_input_delay 1.0 [all_inputs]
set_output_delay 1.0 [all_outputs]

set_load -pin_load 75 [get_ports {xxx*} ]
set_load -pin_load 15 [get_ports {bbb*} ]
set_load -pin_load 15 [get_ports {ggg*}

#*******************************/
# MISC
#*******************************/
current_design design
set_fix_multiple_port_nets -buffer_constants -all
set_cost_priority -delay

current_design design
uniquify
link
compile -map_effort high

#******************************/
# Report Related Information        
#******************************/
current_design design
report_path_group > ./design/report_path_group.rep
report_cell > ./design/report_cell.rep
report_hierarchy > ./design/report_hierarchy.rep
check_design > ./design/check_design.rep
report_area > ./design/report_area.rep

report_timing -group clk_125 -max_paths 20 > ./design/report_timing_clk_125.rep
report_timing -group clk_m -max_paths 20 > ./design/report_timing_clk_m.rep
report_timing -path full -delay max -transition_time -capacitance > ./design/report_timing.rep

report_constraint -max_delay -all_violators > ./design/report_constraint_slack_only.rep
report_constraint -max_delay -verbose -all_violators > ./design/report_constraint.rep
#*****************************/
# Write Netlist & Sdf File   
#*****************************/

ungroup -all -flatten

write -format edif -hierarchy -output ./netlist/design.edif
write -h -f verilog -o ./netlist/design.vgh
write_sdf -version 2.1 -context verilog ./sdf/design.sdf

quit