在UBOOT TINY210V2 S70里实现24BPP的显示CONSOLE 有图有真像
在UBOOT TINY210V2 S7里实现24BPP的显示CONSOLE 有图有真像
代码是关键部分，但不知道为什么背景黑色还是有闪，有哪位高人指点一下。
其它代码没有时间整理，有空了一定上传。
#define GPF0CON (*(volatile unsigned int *)0xE0200120)
#define GPF1CON (*(volatile unsigned int *)0xE0200140)
#define GPF2CON (*(volatile unsigned int *)0xE0200160)
#define GPF3CON (*(volatile unsigned int *)0xE0200180)
#define GPD0CON (*(volatile unsigned int *)0xE02000A0)
#define GPD0DAT (*(volatile unsigned int *)0xE02000A4)
#define CLK_SRC1 (*(volatile unsigned int *)0xe0100204)
#define CLK_DIV1 (*(volatile unsigned int *)0xe0100304)
#define DISPLAY_CONTROL (*(volatile unsigned int *)0xe0107008)
#define VIDCON0 (*(volatile unsigned int *)0xF8000000)
#define VIDCON1 (*(volatile unsigned int *)0xF8000004)
#define VIDCON2 (*(volatile unsigned int *)0xF8000004)
#define WINCON0 (*(volatile unsigned int *)0xF8000020)
#define WINCON1 (*(volatile unsigned int *)0xF8000024)
#define WINCON2 (*(volatile unsigned int *)0xF8000028)
#define WINCON3 (*(volatile unsigned int *)0xF800002C)
#define WINCON4 (*(volatile unsigned int *)0xF8000030)
#define SHADOWCON (*(volatile unsigned int *)0xF8000034)
#define VIDOSD0A (*(volatile unsigned int *)0xF8000040)
#define VIDOSD0B (*(volatile unsigned int *)0xF8000044)
#define VIDOSD0C (*(volatile unsigned int *)0xF8000048)
#define VIDW00ADD0B0 (*(volatile unsigned int *)0xF80000A0)
#define VIDW00ADD1B0 (*(volatile unsigned int *)0xF80000D0)
#define VIDTCON0 (*(volatile unsigned int *)0xF8000010)
#define VIDTCON1 (*(volatile unsigned int *)0xF8000014)
#define VIDTCON2 (*(volatile unsigned int *)0xF8000018)
#define FB_ADDR (0x22000000)
#define COL 800
#define ROW 480
#include "string.h"
#include "uart.h"
#include "text.h"
typedef unsigned char uchar;
typedef unsigned short ushort;
typedef unsigned int uint;
//typedef struct vidinfo {
// ushort vl_col; /* Number of columns (i.e. 160) */
// ushort vl_row; /* Number of rows (i.e. 100) */
// uchar vl_bpix; /* Bits per pixel, 0 = 1 */
//ushort *cmap; /* Pointer to the colormap */
//void *priv; /* Pointer to driver-specific data */
//} vidinfo_t;
#define LCD_WIDTH (COL)
#define LCD_HEIGHT (ROW)
#define LCD_BPP 5
//vidinfo_t panel_info = {
// LCD_WIDTH,
// LCD_HEIGHT,
// LCD_BPP,
// 0,
// 0
//};
/* Calculate nr. of bits per pixel and nr. of colors */
#define NBITS(bit_code) (1 << (bit_code))
#define NCOLORS(bit_code) (1 << NBITS(bit_code))
#define lcd_base (0x22000000)
#define lcd_line_length ((LCD_WIDTH * NBITS (LCD_BPP)) / 8)
void lcd_init(void)
{// GPIO Functional as LCD Signals
GPF0CON = 0x22222222; // GPF0[7:0]
GPF1CON = 0x22222222; // GPF1[7:0]
GPF2CON = 0x22222222; // GPF2[7:0]
GPF3CON = 0x22222222; // GPF3[7:0]
// XpwmTOUT1 GPD0_1 output high level
// GPD0 Control Register (GPD0CON, R/W, Address = 0xE020_00A0)
GPD0CON |= 1<<4;
GPD0DAT |= 1<<1;
// clock init (CLK_SRC1, CLK_DIV1 are optional)
DISPLAY_CONTROL = 2<<0; // 10: RGB=FIMD I80=FIMD ITU=FIMD
// LCD SFR init
// ENVID [1] Video output and the logic immediately enable/disable. ENVID=1，使能lcd控制器
// 0 = Disable the video output and the Display control signal.
// 1 = Enable the video output and the Display control signal.
// ENVID_F [0] Video output and the logic enable/disable at current frame end. 当前帧结束后使能lcd控制器
// 0 = Disable the video output and the Display control signal.
// 1 = Enable the video output and the Display control signal.
// see 210.pdf p1228
VIDCON0 |= 1<<0 | 1<<1 ;
//VIDCON0 &= 0 << 2//选择时钟源为HCLK_DSYS=166MHz;
// CLKVAL_F [13:6] Determine the rates of VCLK and CLKVAL[7:0]
// VCLK = Video Clock Source / (CLKVAL+1) where CLKVAL >= 1
VIDCON0 |= 1<<4;//CLKDIR=1, 选择需要分频
// LCD module para, see H43-HSD043I9W1.pdf p13
VIDCON0 |= 15<<6; // 166M/(14+1) = 11M < 12M(max) 这里写成14也行的！
// LCD module para, see H43-HSD043I9W1.pdf p13
// IHSYNC [6] Specifies the HSYNC pulse polarity.
// 0 = Normal
// 1 = Inverted
// IVSYNC [5] Specifies the VSYNC pulse polarity.
// 0 = Normal
// 1 = Inverted
VIDCON1 |= 1<<5 | 1<<6;
// LINEVAL [21:11]
// HOZVAL [10:0]
VIDTCON2 = (ROW - 1)<<11 | (COL - 1)<<0; // 479*271
// ENWIN_F [0] Video output and the logic immediately enable/disable.
// 0 = Disable the video output and the VIDEO control signal.
// 1 = Enable the video output and the VIDEO control signal.
WINCON0 |= 1<<0;
// BPPMODE_F [5:2] Select the BPP (Bits Per Pixel) mode Window image.
// 1011 = unpacked 24 BPP (non-palletized R:8-G:8-B:8 )
WINCON0 &= ~(0xf << 2);
WINCON0 |= 0xB<<2;
// WSWP_F [15] Specifies the Word swap control bit.
// 0 = Swap Disable
// 1 = Swap Enable
WINCON0 |= 1<<15;
WINCON0 |= 0<<22;
// left top pixel (0, 0)
VIDOSD0A |= 0<<11;
VIDOSD0A |= 0<<0;
// right bottom pixel (479, 271)
VIDOSD0B |= (COL - 1)<<11;
VIDOSD0B |= (ROW - 1)<<0;
VIDOSD0C = (ROW*COL);
// fb address
VIDW00ADD0B0 = FB_ADDR;
VIDW00ADD1B0 = FB_ADDR + ROW * COL * 4;
// LCD module para, see H43-HSD043I9W1.pdf p13
#define HSPW (0)
#define HBPD (46 - 1)
#define HFPD (210 - 1)
#define VSPW (0)
#define VBPD (23 - 1)
#define VFPD (22 - 1)
VIDTCON0 = VBPD<<16 | VFPD<<8 | VSPW<<0;
VIDTCON1 = HBPD<<16 | HFPD<<8 | HSPW<<0;
// LINEVAL [21:11]
// HOZVAL [10:0]
//VIDTCON2 = (ROW - 1)<<11 | (COL - 1)<<0; // 479*271
//C0_EN_F 0 Enables Channel 0.
//0 = Disables 1 = Enables
SHADOWCON = 0x1;
WINCON1 = 0<<0;//关闭WINDOW1
WINCON2 = 0<<0;//关闭WINDOW2
WINCON3 = 0<<0;//关闭WINDOW3
WINCON4 = 0<<0;//关闭WINDOW4
return;
}
