第二章系统架构浏览2.2-2.4小节

2.2 MODES OF OPERATION 操作的模式

The IA-32 supports three operating modes and one quasi-operating mode:

IA32支持下面的三种操作模式和一种类似的模式

• Protected mode — This is the native operating mode of the processor. It

provides a rich set of architectural features, flexibility, high performance and

backward compatibility to existing software base.

保护模式：处理器本身拥有的模式。该模式提供了一个关于架构特性，系统弹性，高速运行以及向后兼容现有软件的丰富集合。

• Real-address mode — This operating mode provides the programming

environment of the Intel 8086 processor, with a few extensions (such as the

ability to switch to protected or system management mode).

实地址模式：这种操作模式提供了intel8086处理器的编程环境，包括一些扩展的特性（比如在保护模式和系统管理模式之间的相互切换）

• System management mode (SMM) — SMM is a standard architectural feature

in all IA-32 processors, beginning with the Intel386 SL processor. This mode

provides an operating system or executive with a transparent mechanism for

implementing power management and OEM differentiation features. SMM is

entered through activation of an external system interrupt pin (SMI#), which

generates a system management interrupt (SMI). In SMM, the processor

switches to a separate address space while saving the context of the currently

running program or task. SMM-specific code may then be executed transparently.

Upon returning from SMM, the processor is placed back into its state prior to the

SMI.

系统管理模式（SMM）：SMM是一种自itel386 SL处理器开始，，所有IA32处理都拥有的标准架构模式。这种模式为操作系统或者程序提供了一种在电源管理，不同设备厂生的不同特性的管理等的透明的架构。SMM模式通过外部中断(SMI#)来激活，激活的同时会产生一个系统管理中断（SMI）。在SMM模式下，处理器在切换至独立的地址空间的时候，会将直接保存当前程序或者当前任务的上下文。当SMM模式返回是，SMM的特定的代码会被透明的执行。？？后面这句不懂。

• Virtual-8086 mode — In protected mode, the processor supports a quasioperating

mode known as virtual-8086 mode. This mode allows the processor

execute 8086 software in a protected, multitasking environment.

Intel 64 architecture supports all operating modes of IA-32 architecture and IA-32e

modes:
虚拟8086模式：在保护模式下，处理器支持一种与保护模式十分类似的模式，这种模式叫虚拟8086模式。

这种模式允许处理去在一个受保护的，多任务的环境中运行8086的程序。Intel64位架构支持所有关于IA32和IA32e的模式。

• IA-32e mode — In IA-32e mode, the processor supports two sub-modes:

compatibility mode and 64-bit mode. 64-bit mode provides 64-bit linear

addressing and support for physical address space larger than 64 GBytes.

Compatibility mode allows most legacy protected-mode applications to run

unchanged.

Figure 2-3 shows how the processor moves between operating modes.

IE32E模式：在IE32E模式下，处理器支持两种子模式：兼容模式和64位模式。64位模式提供64位的线性地址，这使得这种模式可以用于超过64GB的物理地址空间。而兼容模式则允许绝大数在保护模式下合法的程序不经修改即可在该模式上运行。图2-3说明了处理器如何在操作模式间切换。

The processor is placed in real-address mode following power-up or a reset. The PE

flag in control register CR0 then controls whether the processor is operating in realaddress

or protected mode. See also: Section 9.9, “Mode Switching.”

当电源接通或者重启时，处理器是在实地址模式下运行的。CR0控制寄存器里的PE标识控制处理器是在实地址模式下运行，还是在保护模式下运行。查看章节9.9.

The VM flag in the EFLAGS register determines whether the processor is operating in

protected mode or virtual-8086 mode. Transitions between protected mode and

virtual-8086 mode are generally carried out as part of a task switch or a return from

an interrupt or exception handler. See also: Section 15.2.5, “Entering Virtual-8086

Mode.”

EFLAGS寄存器里的VM标识决定处理器是运行在保护模式下，还是运行在虚拟8086模式下。通常，在一个中断或者异常捕捉器返回，或者任务切换时，两种模式的切换就会完成。看章节15.2.5.

The LMA bit (IA32_EFER.LMA.LMA[bit 10]) determines whether the processor is

operating in IA-32e mode. When running in IA-32e mode, 64-bit or compatibility

sub-mode operation is determined by CS.L bit of the code segment. The processor

enters into IA-32e mode from protected mode by enabling paging and setting the

LME bit (IA32_EFER.LME[bit 8]). See also: Chapter 9, “Processor Management and

Initialization.”

（IA32_EFER_LMA_LMA的第十个字节）LMA位决定处理器是否运行在IA32E模式下。代码段的CS.L位决定处理器是运行在IA32E模式下，还是运行在64位模式下，还是运行在兼容模式下。当设置LME位（IA32_EFER_LME的第8个自己）和启用分页时，处理器会自动从保护模式进入到IA32E模式。

看章节9.

The processor switches to SMM whenever it receives an SMI while the processor is in

real-address, protected, virtual-8086, or IA-32e modes. Upon execution of the RSM

instruction, the processor always returns to the mode it was in when the SMI

occurred.

当处理器运行在实地址模式，或是保护模式，或是虚拟8086模式，或是IA32E模式下的时候，一旦处理器收到一个系统管理中断，处理器就会切换至系统管理模式。当RSM指令返回时，处理器总是切换回它在系统管理模式运行之前的模式。

2.3 SYSTEM FLAGS AND FIELDS IN THE EFLAGS

The system flags and IOPL field of the EFLAGS register control I/O, maskable hardware

interrupts, debugging, task switching, and the virtual-8086 mode (see

Figure 2-4). Only privileged code (typically operating system or executive code)

should be allowed to modify these bits.

The system flags and IOPL are:

EFLAGS寄存器里的系统标识符和IO权限等级块控制 I/O，硬件中断的屏蔽，调试，任务切换和虚拟8086模式（看图2-4），只有权限操作代码（以操作系统代码或者程序代码为代表）才被允许修改这些位的值。

下面是系统标识和IO权限控制块的内容：

TF Trap (bit 8) — Set to enable single-step mode for debugging; clear to

disable single-step mode. In single-step mode, the processor generates a

debug exception after each instruction. This allows the execution state of a

program to be inspected after each instruction. If an application program

sets the TF flag using a POPF, POPFD, or IRET instruction, a debug exception

is generated after the instruction that follows the POPF, POPFD, or IRET.

TF陷入（第8位）：设值的时候激活调试的单步执行模式；清零则禁止单步执行模式。在单步执行模式下，处理器会在每条指令执行后产生一个调试异常中断，中断后允许查看每条指令执行后程序的状态。当程序用OPPF,OPOFD,或IRET指令来设置TF标识的时候，POPF,POPFD,IRET后的第一条指令会诱发一个调试异常中断。

IF Interrupt enable (bit 9) — Controls the response of the processor to

maskable hardware interrupt requests (see also: Section 5.3.2, “Maskable

Hardware Interrupts”). The flag is set to respond to maskable hardware

interrupts; cleared to inhibit maskable hardware interrupts. The IF flag does

not affect the generation of exceptions or nonmaskable interrupts (NMI

interrupts). The CPL, IOPL, and the state of the VME flag in control register

CR4 determine whether the IF flag can be modified by the CLI, STI, POPF,

POPFD, and IRET.

IF 中断激活（第9位）：控制处理器对硬件中断屏蔽要求的相应（查看章节5.3.2）。该标识为设值这激活处理器对硬件中断屏蔽的响应，清零这阻止硬件中断屏蔽。IF标识不影响非硬件中断（NMI）和异常。CR4寄存器里的VME标识，和CPL,IPOL一起决定指令CLI,STI,POPF,POPFD,IRET是否能修改IF标识的值。

IOPL I/O privilege level field (bits 12 and 13) — Indicates the I/O privilege

level (IOPL) of the currently running program or task. The CPL of the

currently running program or task must be less than or equal to the IOPL to

access the I/O address space. This field can only be modified by the POPF

and IRET instructions when operating at a CPL of 0.

The IOPL is also one of the mechanisms that controls the modification of the

IF flag and the handling of interrupts in virtual-8086 mode when virtual

mode extensions are in effect (when CR4.VME = 1). See also: Chapter 13,

“Input/Output,” in the Intel® 64 and IA-32 Architectures Software Developer’s

Manual, Volume 1.

I/O权限等级快（位12和位13）：这两个位表明了当前运行的程序或任务的I/O权限等级。当前程序或任务的处理器权限等级（CPL）一定要比前程序或任务要访问的I/O地址空间的I/O权限等级要低。只有指令OPPF和IRET在处理器权限等级0的状态下才能修改这块的数值。查看章节13.

NT Nested task (bit 14) — Controls the chaining of interrupted and called

tasks. The processor sets this flag on calls to a task initiated with a CALL

instruction, an interrupt, or an exception. It examines and modifies this flag

on returns from a task initiated with the IRET instruction. The flag can be

explicitly set or cleared with the POPF/POPFD instructions; however,

changing to the state of this flag can generate unexpected exceptions in

application programs.

See also: Section 6.4, “Task Linking.”

NT内嵌任务（位14）：控制被中断任务和被调用任务的链。当通过指令CALL，中断，或是异常调用任务时，处理器就会设置该标识的值。当一个任务通过IRET指令返回时，处理器会检查和修改该标识的值。虽然可以通过POPF/IRET指令来设置或清零该标识的值，但改变这个标识的状态可能会引发一些程序的意外的异常。

RF Resume (bit 16) — Controls the processor’s response to instruction-breakpoint

conditions. When set, this flag temporarily disables debug exceptions

(#DB) from being generated for instruction breakpoints (although other

exception conditions can cause an exception to be generated). When clear,

instruction breakpoints will generate debug exceptions.

The primary function of the RF flag is to allow the restarting of an instruction

following a debug exception that was caused by an instruction breakpoint

condition. Here, debug software must set this flag in the EFLAGS image on

the stack just prior to returning to the interrupted program with IRETD (to

prevent the instruction breakpoint from causing another debug exception).

The processor then automatically clears this flag after the instruction

returned to has been successfully executed, enabling instruction breakpoint

faults again.

See also: Section 18.3.1.1, “Instruction-Breakpoint Exception Condition.”

RF(重设)（位16）：该标识控制处理器对指令的断点情况的响应。该标识设值就会暂时禁止指令断点产生调试异常（虽然其他的异常会诱发产生一个异常）；清零的时候，激活指令断点产生调试异常。指令断点状态产生的异常，可以在调试异常后的第一条指令，通过RF标识的函数重新诱发。调试中的程序必须在程序因为IRETD而中断返回之前，设置栈里的EFLAGS寄存器镜像的RF标识（防止指令断点引发另外一个调试异常）。处理器会在返回指令成功执行后，自动清零该标识，并且重新激活指令错误。

VM Virtual-8086 mode (bit 17) — Set to enable virtual-8086 mode; clear to

return to protected mode.

See also: Section 15.2.1, “Enabling Virtual-8086 Mode.”

VM 虚拟8086模式（位17）：设值则激活虚拟8086模式，清零则返回保护模式。查看章节15.2.1.

AC Alignment check (bit 18) — Set this flag and the AM flag in control register

CR0 to enable alignment checking of memory references; clear the AC flag

and/or the AM flag to disable alignment checking. An alignment-check

exception is generated when reference is made to an unaligned operand,

such as a word at an odd byte address or a doubleword at an address which

is not an integral multiple of four. Alignment-check exceptions are generated

only in user mode (privilege level 3). Memory references that default to privilege

level 0, such as segment descriptor loads, do not generate this exception

even when caused by instructions executed in user-mode.

The alignment-check exception can be used to check alignment of data. This

is useful when exchanging data with processors which require all data to be

aligned. The alignment-check exception can also be used by interpreters to

flag some pointers as special by misaligning the pointer. This eliminates

overhead of checking each pointer and only handles the special pointer when

used.

AC 数据对齐检查（位18）通过设置CR0控制寄存器中的该标识和AM标识，可以激活内存引用的数据对齐检查，清零该标识（AM清零不是必须的）则禁止数据对齐检查。当内存引用的数据是由无法直接构成对齐的操作数组成的时候，一个数据对齐异常便会产生，比如零碎地址上的一个字，或者不是四的倍数的地址上的一个双字。数据对齐异常只会在用户模式（等级3）下产生。因为用户模式下的指令执行而导致的，类似段描述符导入等在等级0上的内存数据引用，是不会诱发数据对齐异常的。

数据对齐异常可以用于检查数据的对齐。因为处理器要求所有数据必须对齐，因此，在和处理器交换数据时，进行数据对齐的检查，是非常有用的。在解释程序标明一些特殊的指针，比如调整指针的位置时，通过使用数据对齐异常，可以不必对每个指针进行过度的检查，只需处理正在使用的特殊指针。？？

VIF Virtual Interrupt (bit 19) — Contains a virtual image of the IF flag. This

flag is used in conjunction with the VIP flag. The processor only recognizes

the VIF flag when either the VME flag or the PVI flag in control register CR4 is

set and the IOPL is less than 3. (The VME flag enables the virtual-8086 mode

extensions; the PVI flag enables the protected-mode virtual interrupts.)

See also: Section 15.3.3.5, “Method 6: Software Interrupt Handling,” and

Section 15.4, “Protected-Mode Virtual Interrupts.”

VIF 虚拟终端（位19）：包含了IF标识的一个虚拟镜像。VIF标识和VME标识一起使用。只有当IOPL的权限等级小于3，并且CR4控制寄存器里的整个VME标识或者整个PVI标识被设值，处理器才会识别VIF标识。（VME标识激活虚拟8086模式的扩展特性；PVI标识激活保护模式的虚拟终端）。度章节15.3.3.5.

VIP Virtual interrupt pending (bit 20) — Set by software to indicate that an

interrupt is pending; cleared to indicate that no interrupt is pending. This flag

is used in conjunction with the VIF flag. The processor reads this flag but

never modifies it. The processor only recognizes the VIP flag when either the

VME flag or the PVI flag in control register CR4 is set and the IOPL is less than

3. The VME flag enables the virtual-8086 mode extensions; the PVI flag

enables the protected-mode virtual interrupts.

VIP 虚拟中断等待（位20）：该标识表明一个中断被等待，且该位是通过程序来设值得。清零表明无中断被等待。该标识和VIF标识一起使用。处理会读取该标识但从来不修改标识的值。只有IOPL等级小于3，并且CR4控制寄存器里的VME标识或者PVI标识被设值，处理器才会识别该标识。VME标识激活虚拟8086的扩展特性，PVI标识激活保护模式的虚拟终端。

ID Identification (bit 21). — The ability of a program or procedure to set or

clear this flag indicates support for the CPUID instruction.

ID 身份验证(位21)：程序可以对该标识设值或者清零。该标识用以表明对CPUID指令的支持。

2.3.1 System Flags and Fields in IA-32e Mode（IA32E模式的系统标识和系统标识块）

In 64-bit mode, the RFLAGS register expands to 64 bits with the upper 32 bits

reserved. System flags in RFLAGS (64-bit mode) or EFLAGS (compatibility mode)

are shown in Figure 2-4.

在64模式下，EFLAGS寄存器扩展至64位，而高32位是保留的。EFLAGS寄存器里的系统标识如图2.4所示。

In IA-32e mode, the processor does not allow the VM bit to be set because virtual-

8086 mode is not supported (attempts to set the bit are ignored). Also, the processor

will not set the NT bit. The processor does, however, allow software to set the NT bit

(note that an IRET causes a general protection fault in IA-32e mode if the NT bit is

set).

虚拟8086模式不支持VM标识，故在IA32E模式下，处理器不允许设置VM标识（即使设置也会被忽略）。

同样，处理器也不设置NT位.但是允许软件设置NT位（如果NT被设值，IRET会诱发一个保护错误）

In IA-32e mode, the SYSCALL/SYSRET instructions have a programmable method of

specifying which bits are cleared in RFLAGS/EFLAGS. These instructions save/restore

EFLAGS/RFLAGS.

在IA32E模式下，指令SYSCALL/SYSRET都有一个可编程的方法来识别RFLAGS/EFLAGS寄存器里的那些位被清零了。这些指令可以保存/重新保存EFLAGS/RFLAGS的值。

2.4 MEMORY-MANAGEMENT REGISTERS内存管理寄存器

The processor provides four memory-management registers (GDTR, LDTR, IDTR,

and TR) that specify the locations of the data structures which control segmented

memory management (see Figure 2-5). Special instructions are provided for loading

and storing these registers.

处理器提供了四个内存管理寄存器（GDTR,LDTR,IDTR,和TR）,这些寄存器用于查询控制分段内存管理的数据结构的位置。（看图2-5）一些特别的指令用于导入和保存这些寄存器的值。

2.4.1 Global Descriptor Table Register (GDTR)全局描述符符表寄存器

The GDTR register holds the base address (32 bits in protected mode; 64 bits in

IA-32e mode) and the 16-bit table limit for the GDT. The base address specifies the

linear address of byte 0 of the GDT; the table limit specifies the number of bytes in

the table.

全局描述符表寄存器由基地址（保护模式为32位，IA32E位64位），16位表长限制组成。基地址指明GDT的第0个字节的线性地址；表长限制指明表里的字节数目。

The LGDT and SGDT instructions load and store the GDTR register, respectively. On

power up or reset of the processor, the base address is set to the default value of 0

and the limit is set to 0FFFFH. A new base address must be loaded into the GDTR as

part of the processor initialization process for protected-mode operation.

See also: Section 3.5.1, “Segment Descriptor Tables.”

指令LGDT和SGDT用以导入和保存GDTR寄存器。当电源接通或者处理重启时，GDT的基地值设置成默认值0，而表长限制被设置成OFFFFH。保护模式下，作为处理器初始化进程的一部分，GDTR的新地址必须被导入。

2.4.2 Local Descriptor Table Register (LDTR)局部描述符表寄存器

The LDTR register holds the 16-bit segment selector, base address (32 bits in

protected mode; 64 bits in IA-32e mode), segment limit, and descriptor attributes

for the LDT. The base address specifies the linear address of byte 0 of the LDT

segment; the segment limit specifies the number of bytes in the segment. See also:

Section 3.5.1, “Segment Descriptor Tables.”

LDTR寄存器由16段选择器，基地址（保护模式为32位，IA32E模式为64位）,段长限制，以及LDT的描述符属性组成。基地值知名LDT的第0字节的线性地址。段长限制知名段的字节数目；

The LLDT and SLDT instructions load and store the segment selector part of the LDTR

descriptor in the GDT. When the LLDT instruction loads a segment selector in the

LDTR: the base address, limit, and descriptor attributes from the LDT descriptor are

automatically loaded in the LDTR.

指令LLDT和SLDT用于导入和保存LDTR的段选择器部分。包含LDT的段用于一个在GDT里的段描述符。当LLDT指令导入LDTR里的段选择器的时候，基地址，段长显示，描述符属性会给自动导入到LDTR里。

When a task switch occurs, the LDTR is automatically loaded with the segment

selector and descriptor for the LDT for the new task. The contents of the LDTR are not

automatically saved prior to writing the new LDT information into the register.

On power up or reset of the processor, the segment selector and base address are set

to the default value of 0 and the limit is set to 0FFFFH.

发生任务切换时，新任务的LDT里的段选择器，描述符自动导入LDTR里。在将新的LDT信息写入到寄存器之前，LDTR里的内容不会自动保存。电源接通或者处理器重启，选择器和基地址被设置成默认值0，段长限制被设置成0FFFFH。

2.4.3 IDTR Interrupt Descriptor Table Register IDTR中断描述符表寄存器

The IDTR register holds the base address (32 bits in protected mode; 64 bits in

IA-32e mode) and 16-bit table limit for the IDT. The base address specifies the linear

address of byte 0 of the IDT; the table limit specifies the number of bytes in the table.

The LIDT and SIDT instructions load and store the IDTR register, respectively. On

power up or reset of the processor, the base address is set to the default value of 0

and the limit is set to 0FFFFH. The base address and limit in the register can then be

changed as part of the processor initialization process.

See also: Section 5.10, “Interrupt Descriptor Table (IDT).”

IDTR寄存器由基地址（保护模式为32位，IA32E模式为64位），16位IDT表长限制组成。基地址知名IDT的第0个字节的线性地址。表长限制指明表的字节数目。指令LIDT和SIDT分别用于导入和保存IDTR寄存器里的值。电源接通或者处理器重启时，基地址被设置成默认值0，段长限制被设置成0FFFFH。处理器初始化进程时，作为初始化的一部分，寄存器里的基地址和段长显示可以发生变化。

2.4.4 Task Register (TR) 任务寄存器

The task register holds the 16-bit segment selector, base address (32 bits in

protected mode; 64 bits in IA-32e mode), segment limit, and descriptor attributes

for the TSS of the current task. The selector references the TSS descriptor in the GDT.

The base address specifies the linear address of byte 0 of the TSS; the segment limit

specifies the number of bytes in the TSS. See also: Section 6.2.4, “Task Register.”

The LTR and STR instructions load and store the segment selector part of the task

are automatically loaded into the task register. On power up or reset of the processor,

the base address is set to the default value of 0 and the limit is set to 0FFFFH.

When a task switch occurs, the task register is automatically loaded with the

segment selector and descriptor for the TSS for the new task. The contents of the

task register are not automatically saved prior to writing the new TSS information

into the register.

任务寄存器由16位段选择器，基地址（保护模式为32位，IA32E模式为64位），段长限制，以及当前任务的任务状态段的段描述符属性组成。选择器指向GDT里的任务状态段的描述符。基地址指明任务状态段的第0个字节的线性地址。

指令LTR和STR分别用于导入和保存任务寄存器里的段选择器部分。使用LTR指令导入任务寄存器的段选择器的时候，TSS描述符的属性，基地址，段长显示会被自动导入。电源接通或处理器重启时，基地址被设置成默认值0，段长限制被设置成0FFFFH。发生任务切换时，新任务的任务状态段的段选择器和描述符会被自动导入到TR寄存器中。在新任务的TSS信息导入到寄存器之前，TR寄存器里面的内容不会被自动保存。

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