the Power Management Module of ADSP

Subject: some problems about the "Power Management"

Dir Sir:

I am very sorry to bother you! But I really have some problems about the "Power Management"  while we using the EZ-KIT of BF561.

Our corporation has bought 2 pieces of USB-LAN and 2 pieces of BF561 from your company. We use BF561 for video encoding (H.264), we create our framework from the example of JPEG-MJPEG-SDK (for VDSP++ 4.0).

 

1. The update of VisualDSP++ 4.0 we are using is                June 2006 Update

 

2. the Board Revision of BF561 EZ-KIT                                Revision 1.3  2004

    the Silicon Revision of the BF561                                    BF561  "U44"  2.0

    the Board Revision of the USB-LAN EZ-Extender              Revision 2.0  2004

 

Now we are using both of coreA and coreB for encoding and the program can run succeessfully.

 

But now I find that at the latest version of the JPEG-MJPEG-SDK (BlackfinSDK-Rel200) , there has a function of ezInitPower(1) which is used for the Power Management.

 

We want to add this funtion to our framework, but after adding this funtion, the program can not run succeessfully.

 

// ezInitPower(1); // the program can not run succeessfully after adding this function
// ezInitPower(2); // the program can not run succeessfully after adding this function

 

We don't know why and we are ergently look forward to your answers, thanks very much!
                                                                                              

                                                                                                              Quanming Wang

 

Hi,

We strongly recommend that you install the VisualDSP 4.5 November update, to get the latest system services and device drivers.  Please refer to the "System Services and Device Drivers" manual in VisualDSP Help.  It explains how to initialize power management and EBIU by calling the functions "adi_pwr_Init" and "adi_ebiu_Init".   You may find it helpful to view the video tutorial on system services:  http://my.analog.com/onlinetraining/boldlist.html

 

The power management section of the 'System Services and Device Drivers' manual explains dual core synchronization for the ADSP-BF561.  On the ADSP-BF561, BOTH CORES must call 'adi_pwr_init()', while only one core needs to call 'adi_ebiu_init()'.  In your application, it appears that core B is not calling 'adi_pwr_Init()', so the cores are not synchronized.

 

The attached files demonstrate  the recommended way to initialize system services, for each processor.  For the ADSP-BF561 use the code within the  #if defined(__ADSP_TETON__) clauses.    

 

Also, below is an example of initializing EBIU and power management on Core A and Core B, so that the two cores are synchronized during power initialization, and will subsequently be synchronized whenever changes are applied to SDRAM.  Please also refer to the power management example which is in the VisualDSP 4.0 installation directory: in ".../ Blackfin/EZ-KITs/ADSP-BF561/Services/PowerManagement/PowerDemo1/DualCore" and also in the VisualDSP 4.5 installation directory, in ".../Blackfin/Examples/ADSP-BF561 EZ-KIT Lite/Services/PowerManagement/PowerDemo/DualCore".

 

CORE A:

-------------

 

 // initialize the Interrupt Manager

 

 u32 ResponseCount;

 ezErrorCheck(adi_int_Init(IntMgrData, sizeof(IntMgrData), &ResponseCount, NULL));
 
 // Initialize other system services, as needed

 

// Then initialize EBIU

 

 ADI_EBIU_RESULT EBIUResult;
 
 ADI_EBIU_COMMAND_PAIR ezkit_sdram[] = { 
  { ADI_EBIU_CMD_SET_SDRAM_BANK_SIZE,  (void*)&bank_size       },
  { ADI_EBIU_CMD_SET_SDRAM_BANK_COL_WIDTH,(void*)&bank_caw      },
  { ADI_EBIU_CMD_SET_SDRAM_CL_THRESHOLD, (void*)100000000        },
  { ADI_EBIU_CMD_SET_SDRAM_TRASMIN,  (void*)&ebiu_44_nanosecs    },
  { ADI_EBIU_CMD_SET_SDRAM_TRPMIN,  (void*)&ebiu_20_nanosecs    },
  { ADI_EBIU_CMD_SET_SDRAM_TRCDMIN,  (void*)&ebiu_20_nanosecs    },
  { ADI_EBIU_CMD_SET_SDRAM_TWRMIN,  (void*)&twr_min          },
  { ADI_EBIU_CMD_SET_SDRAM_REFRESH,  (void*)&sdram_refresh   },
  // The next command disables Fast back to back read/write sequences
  // which is safe for all systems
  { ADI_EBIU_CMD_SET_SDRAM_FBBRW,   (void*)0     },
  { ADI_EBIU_CMD_END, 0}
 };
 
  // Pass the above table to the Initialization routine
 
 EBIUResult = adi_ebiu_Init( ezkit_sdram, DO_NOT_CHANGE_MMR_SETTINGS );
 if ((EBIUResult != ADI_EBIU_RESULT_SUCCESS) && (EBIUResult != ADI_EBIU_RESULT_CALL_IGNORED)) {
  ezErrorCheck(1);
 } 

 

// Initialize power management

 

  ADI_PWR_RESULT  PWRResult;
 
 // The following command table describes the configuration for the ADSP-BF561 EZ-KIT.

 ADI_PWR_COMMAND_PAIR ezkit_power[] = { 
  { ADI_PWR_CMD_SET_PROC_VARIANT,  (void*)ADI_PWR_PROC_BF561SKBCZ500X }, // Processor variant
  { ADI_PWR_CMD_SET_PACKAGE,       (void*)ADI_PWR_PACKAGE_MBGA        },   // Packaging type of processor
  { ADI_PWR_CMD_SET_VDDEXT,        (void*)ADI_PWR_VDDEXT_330          }, // External voltage supply (3.3V)
  { ADI_PWR_CMD_SET_CLKIN,         (void*)30 /* MHz */                },   // 30Mhz oscillator connected to CLKIN
  { ADI_PWR_CMD_SET_AUTO_SYNC_ENABLED,(void*)0            },   // Enable Dual Core Synchronization
  { ADI_PWR_CMD_END, (void*)0}           // No more commands
 }; 

 

 // Pass the above table to the Initialization routine
 
 PWRResult = adi_pwr_Init( ezkit_power );
 if ((PWRResult != ADI_PWR_RESULT_SUCCESS) && (PWRResult != ADI_PWR_RESULT_CALL_IGNORED)) {
  ezErrorCheck(1);
 }

 

 // set the processor to give the fastest clock frequencies for the
 // lowest voltage level.
 
 adi_pwr_SetMaxFreqForVolt( ADI_PWR_VLEV_070 );

----------------------------------------------------------------------------

CORE B:

-------------

 

// Initialize power management Only

 

  ADI_PWR_RESULT  PWRResult;
 
 // The following command table describes the configuration for the ADSP-BF561 EZ-KIT.

 ADI_PWR_COMMAND_PAIR ezkit_power[] = { 
  { ADI_PWR_CMD_SET_PROC_VARIANT,  (void*)ADI_PWR_PROC_BF561SKBCZ500X }, // Processor variant
  { ADI_PWR_CMD_SET_PACKAGE,       (void*)ADI_PWR_PACKAGE_MBGA        },   // Packaging type of processor
  { ADI_PWR_CMD_SET_VDDEXT,        (void*)ADI_PWR_VDDEXT_330          }, // External voltage supply (3.3V)
  { ADI_PWR_CMD_SET_CLKIN,         (void*)30 /* MHz */                },   // 30Mhz oscillator connected to CLKIN
  { ADI_PWR_CMD_SET_AUTO_SYNC_ENABLED,(void*)0            },   // Enable Dual Core Synchronization
  { ADI_PWR_CMD_END, (void*)0}           // No more commands
 }; 

 

 // Pass the above table to the Initialization routine
 
 PWRResult = adi_pwr_Init( ezkit_power );
 if ((PWRResult != ADI_PWR_RESULT_SUCCESS) && (PWRResult != ADI_PWR_RESULT_CALL_IGNORED)) {
  ezErrorCheck(1);
 }

 

 // set the processor to give the fastest clock frequencies for the
 // lowest voltage level.
 
 adi_pwr_SetMaxFreqForVolt( ADI_PWR_VLEV_070 );

-------------------------------------------------------------------------------------------------------------

 

By the way, you mentioned that you have the "BlackfinSDK-Rel200".  This should not install over VisualDSP 4.0, so this may be a problem, as the "BlackfinSDK-Rel200" installation requires the VisualDSP 4.5 November update.  The examples and utility functions contained in that installation depend on the presence of the VisualDSP 4.5 libraries.  It would be best to upgrade to VisualDSP 4.5 and install the November update and look at the example:  ".../Program Files/Analog Devices/VisualDSP 4.5/Blackfin/Examples/ADSP-BF561 EZ-KIT Lite/Services/PowerManagement/PowerDemo/DualCore". 

 

For your information, the functions "ezInit()" and "ezInitPower()" are provided in some examples to simplify the initialization of power and EBIU. The "ezInit()" function initializes Asynch memory, power management and EBIU.  Then it calls the "ezInitPower()" function, which ultimately calls "adi_pwr_Init()".  The argument passed to "ezInit()" function indicates the number of cores.  With two cores, that argument would be 2.  The important thing to note is that the function should be called by BOTH CORES, to ensure that they both are IDLE when power management is initialized and whenever changes are applied to the EBIU.  The linker description file (LDF) must allocate space in shared memory for a synchronization lock variable, to be used by the supplemental ISR that synchronizes the cores.  The LDF in the powerdemo example demonstrates this.

 

We hope this information is helpful.

 

Regards,

Processor Tools Support