zedboard--PlanAhead不能生成bit文件

用PlanAhead来生成bit文件，几天一直在出现这个错误，却找不出来：

[Bitgen 342] This design contains pins which have locations (LOC) that are not user-assigned or I/O Standards (IOSTANDARD) that are not user-assigned. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To prevent this error, it is highly suggested to specify all pin locations and I/O standards to avoid potential contention or conflicts and allow proper bitstream creation. To demote this error to a warning and allow bitstream creation with unspecified I/O location or standards, you may apply the following bitgen switch: -g UnconstrainedPins:Allow
 
[Bitgen 157] Bitgen will terminate because of the above errors.

解决办法：

1.检查ucf文件是否有非法字符，这个有一部分是这个原因，电平标准之类。

  

2.如果依旧出错，就有可能是下面这种情况了，

在一论坛上看到了这样的解法：论坛地址

http://forums.xilinx.com/xlnx/board/crawl_message?board.id=7Series&message.id=1769

Did you specify LOC and IO standard constraints for all top level ports in your design?
 
If not, it is recommended to do that. If you want to overcome the error message without specifying the LOCs as said before you can specify the switch  -g UnconstrainedPins:Allow in More options field of Bitstream settings as shown below and re-running bitgen.

你有没有在你的设计中的所有顶层端口指定LOC和IO标准的约束？
 
如果没有，建议这样做。如果你想克服错误信息，而无需指定交通线如之前所说，您可以指定开关-G UnconstrainedPins：允许在比特流的设置，如下图所示，然后重新运行更多BitGen的选项字段。

在给用户ip核写一个裸机应用程序时，他的作用我认为是验证我们的ip核是不是正常工作，我在写这个应用程序的时候，总是在第一次不能成功，就像博客里说的先出现一次错误，在重新写一个应用程序就行（一模一样）

http://blog.csdn.net/xzyiverson/article/details/12889521